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Name	Direction	Clock domain	Width	Description
Clock logic
axiClk	Input	-	1	AXI Lite clock
axiRst	Input	axiClk	1	AXI Lite reset
devClk_i	Input	-	1	Development clock
devRst_i	Input	Synced to devClk_i in DaqMux (for some reason)	1	Development logic reset
wfClk_i	Input	-		Ouput lanes' clock
wfRst_i	Input	wfClk_i		Output lanes' reset
DaqMux control signals and timing information
trigHw_i	Input	Synced to devClk_i in DaqMux	1	Trigger signal to start the DaqMux streaming 0 indicates no trigger event 1 indicates a trigger event
trigCasc_i	Input	Synced to devClk_i in DaqMux	1	Cascaded trigger input. Can be used along with trigHw_i when enabled in the register file 0 indicates no trigger event 1 indicates a trigger event
trigCasc_o	Output	devClk_i	1	Output trigger signal connected to the SW Trigger Enable control register 0 indicates no trigger event 1 indicates a trigger event
armCasc_i	Input	Synced to devClk_i in DaqMux	1	Cascaded trigger Arm. Arms the trigger and prepares DaqMux for trigger arrival 0 indicates no arm 1 indicates armed
armCasc_o	Output	-	1	Output cascade signal connected to the Arm HW Trigger control register 0 indicates no arm 1 indicates armed
freezeHw_i	Input	Synced to devClk_i in DaqMux	1	Adds invalid flag to the streams that are forwarded, and they will be discarded in one of the posterior blocks in the pipeline 0 indicates valid (not freeze) 1 indicates invalid (freeze)
timeStamp_i	Input	Synced to devClk_i in DaqMux	64	Time stamp coming from the AMC carrier core
bsa_i	Input	Synced to devClk_i in DaqMux	128	BSA information coming from the AMC carrier core
dmod_i	Input	Synced to devClk_i in DaqMux	192	Dmod timing information coming from the AMC carrier core
AXI Lite register memory mapped interface for reading and writing to register file
axilReadMaster	Input	axiClk	1	AXI Lite record containing Read Address channel araddr : slv(31 downto 0); arprot : slv(2 downto 0); arvalid : sl; Read data channel rready : sl;
axilReadSlave	Output	axiClk	1	AXI Lite record containing Read Address channel arready : sl; Read data channel rdata : slv(31 downto 0); rresp : slv(1 downto 0); rvalid : sl;
axilWriteMaster	Input	axiClk	1	AXI Lite record containing Write address channel awaddr : slv(31 downto 0); awprot : slv(2 downto 0); awvalid : sl; Write data channel wdata : slv(31 downto 0); wstrb : slv(3 downto 0); wvalid : sl; Write ack channel bready : sl;
axilWriteSlave	Output	axiClk	1	AXI Lite record containing Write address channel awready : sl; Write data channel wready : sl; Write ack channel bresp : slv(1 downto 0); bvalid : sl;
Input lane array - data valid based
sampleDataArr_i	Input	devClk_i	N_DATA_IN_G	Input data stream array of 32-bit words
sampleValidVec_i	Input	devClk_i	N_DATA_IN_G	Input valids with each valid corresponding to the respective stream in that cycle
linkReadyVec_i	Input	devClk_i	N_DATA_IN_G	Indicate that the stream source is ready. If is 0, the DaqMux sets the Stream Error control register to 1
Output lane array
rxAxisMasterArr_o	Output	wfClk_i	N_DATA_OUT_G	AXI compliant output data stream array of 32-bit words. Nonetheless, the type of rxAxisMasterArr_o is defined as follows in the AxiStreamPkg.vhd file tValid : sl; tData : slv(511 downto 0); tStrb : slv(63 downto 0); tKeep : slv(63 downto 0); tLast : sl; tDest : slv(7 downto 0); tId : slv(7 downto 0); tUser : slv(63 downto 0);
rxAxisSlaveArr_i	Input	wfClk_irxAxisCtrlArr_i	N_DATA_OUT_G	AXI streams data ready signals
	Input	wfClk_i	N_DATA_OUT_G	AXI stream control signals as follows pause : sl; overflow : sl; idle : sl; If pause is 1, the DaqMux will not start and error is set.

rxAxisMasterArr_o

Functional description & block diagrams

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Functional description & block diagrams