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The frame received by software will contain a series of trigger frames as output from the Firmware Event Builder. The number of event builder frames will be determined by the configured block size (N). 

These frames will be formed into a larger frame using the SLAC Stream Batcher protocol.

First a single Frame Trigger Block Header will be included for each  

• Trigger Block

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• Frame Header (64-bits)
  • Frame Trigger Block Header Word 0 (32-bits) 
    • 31:16 = 0x0000
    • 15:08 = Sequence # (running, spans each run)
    • 07:04 = 0x2 (64-bits)
    • 03:00 = 0x1 (version 1)
  • Frame Trigger Block Header Word 1 (32-bits)
    • 31:00 = 0x00000000

Next will be N data sections, one for each trigger. Each section will have a contain the Event Builder Header, N MultiSamples and 64-bit tail.

• • Event Builder Header 0 (32-bits)
    • 31:00 = Event Counter
  • Event Builder Header 1 (32-bits)
    • 31:08 = 0x000000
    • 07:00 = RCE Address
  • MultiSample Data ( N * 4 * 32-bits)
  • Per Trigger Tail Word 0 (32-bits)
    • 31:00: Number of valid bytes in data section, excluding tail (2 * 4 + N * 16)
  • Per Trigger Tail Word 1 (32-bits)
    • 31:24: 0x7 (Number of valid bytes last 64-bit word) (can be ignored)
    • 23:17: 0x00 (Unused TUSER_LAST)
    • 16: Error Flag
    • 15:08: 0x00 (Unused TUSER_FIRST)
    • 07:00: 0x00 (Unused TDEST Field)
      
      
      
      

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