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Code Block
Got Response: 
Got Response: Model          P4_CM_02K10D_00_R
Got Response: Microcode      03-081-20296-13
Got Response: CCI            03-110-20294-03
Got Response: FPGA           03-056-20470-03
Got Response: Serial #       12102856
Got Response: BiST:          Good
Got Response: 
Got Response: DefaultSet     1
Got Response: Ext Trig       Off
Got Response: Trig Overlap   Off
Got Response: Line Rate      1 [Hz]
Got Response: Meas L.R.      6 [Hz]
Got Response: Max  L.R.      19607 [Hz]
Got Response: Exp. Mode      Timed 
Got Response: Multi Exp. Mode   Off 
Got Response: Exp. Time[0]   50000 [ns]
Got Response: Meas E.T.[0]   50000 [ns]
Got Response: Max  E.T.      3000500 [ns]
Got Response: 
Got Response: Test Pat.      1:Ramp1
Got Response: Direction      Internal, Forward
Got Response: TDI Stages     2
Got Response: Vert. Bin      1
Got Response: Hor. Bin       1
Got Response: Flat Field     Off
Got Response: Offset         0
Got Response: System Gain    1.00
Got Response: Mirror         Off
Got Response: AOI Mode:      Off
Got Response: Scan Type      Line Scan
Got Response: CL Speed       85MHz
Got Response: CL Config      Medium
Got Response: Pixel Fmt      8 bits
Got Response: CPA ROI        1-2048

Notes From Matt On Evr Firmware

wrapper to transceivers:

https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingGthWrapper.vhd

decoding the output:

https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingCore.vhd

this record has a strobe that says when it's valid:
appTimingBus : out TimingBusType;

has the record structure:

https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingPkg.vhd

strobe : sl; -- which clock cycle it is valid
valid : sl; --
message : TimingMessageType; -- for lcls-II
stream : TimingStreamType; -- for lcls-I (eventcodes in this record)
v1 : LclsV1TimingDataType;
v2 : LclsV2TimingDataType;
modesel : sl; -- LCLS-II selected -- tells us the mode, another register sets it

axi-stream: amba-xilinx-interconnect: no address involved, like a port, push/acknowledge
axi: full memory interface: address/values and can burst multiple values
axi-lite: used for register interfaces: 32-bit value with address