Page History

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Support an AXI4-Lite and AXI4 firmware modules
- SrpV3AxiLite.vhd will only support 32-bit transactions and 32-bit alignment
- For applications that need non 32-bit transactions or non 32-bit alignment for AXI-Lite, we can achieve this by bridging the SrpV3Axi.vhd with the AxiToAxiLite.vhd
Echos back the AXI stream's TDEST
Header will include:
- SRP Version number: (8-bits)
  - Always echo backs the local version (0x03)
- OP-Code: Non-Posted Read, Non-Posted Write, Posted Write, NULL (2-bit)
- Non 32-bit address alignment support (1-bit)
- Non 32-bit transaction alignment support (1-bit)
- Spare Reserved (12-bit)
- Timeout counter (8-bit)
  - In units of 100 ms
  - If 0x0, no time out
- Transaction ID: (32-bits)
- Base Address of bursting (64-bits)
- Request Size (32-bit)
  - In units of bytes
  - Max. read size is 2³²
  - Max. write size is 2¹²
Header will be echoed except for:
- SRP Verson number
Footer will be 32-bit, zero on success, and will include:
- Memory Bus response (8-bit)
  - success == 0x0
  - failed != 0x0
- Timeout flag (1-bit)
- Request's EOFE (1-bit)
- Version Mismatch (1-bit)
- Invalid request size (1-bit)
- All other bits must be 0x0

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Word#	BITS	Name	Description	Note
0	[7:0]	Version[7:0]	SRP Version number
0	[9:8]	OpCode[1:0]	Operation Code	0x0=Non-Posted Read 0x1=Non-Posted Write 0x2=Posted Write 0x3=NULL
0	[1123:10]	Reserved	Reserved	Ignored
0[23:12]	SPARE[11:0]			0	[31:24]	TimeoutCnt[7:0]	Timeout Counter	If 0x00, then no timeout In units of 100 ms
1	[31:0]	TID[31:0]	Transaction ID
2	[31:0]	Addr[31:0]	Register Address	In units of bytes
3	[31:0]	Addr[63:32]	Register Address	In units of bytes
4	[31:0]	ReqSize[31:0]	Request Size	In units of bytes Counting from zero ReqSize = 0x0 is 1 byte request
5	[31:0]	WriteData[31:0]	Write Data	Only used for write operations
...	...	...	...	Only used for write operations
4+CEIL((ReqSize+1)/4)	[31:0]	WriteData[31:0]	Write Data	Only used for write operations

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Word#	BITS	Name	Description	Note
0	[7:0]	Version[7:0]	Module's SRP Version number	Always respond with local value
0	[9:8]	OpCode[1:0]	Operation Code	Echoed back
0	[10]	AddressAccess	Module's non 32-bit address access support	Always respond with local value 0 = not supported (only 32-bit alignment) 1 = supported (byte alignment)
0	[11]	TransactionAccess	Module's non 32-bit transaction support	Always respond with local value 0 = not supported (only 32-bit transactions) 1 = supported (byte level transactions)
0	[23:10]	SPARE[13:0]	Unused, spare bits	Reserved	Reserved	Responses back with 0x0Echoed back
0	[31:24]	TimeoutCnt[7:0]	Timeout Counter	Echoed back
1	[31:0]	TID[31:0]	Transaction ID	Echoed back
2	[31:0]	Addr[31:0]	Register Address	Echoed back
3	[31:0]	Addr[63:32]	Register Address	Echoed back
4	[31:0]	ReqSize[31:0]	Request Size	Echoed back
5	[31:0]	MemData[31:0]	Memory Data	Only used for non-posted operations
...	...	...	...	Only used for non-posted operations
4+CEIL((ReqSize+1)/4)	[31:0]	MemData[31:0]	Memory Data	Only used for non-posted operations
5+CEIL((ReqSize+1)/4)	[7:0]	MemResp[7:0]	Memory Bus Response	Footer : if MemResp == 0, then success if MemResp != 0, then failed
5+CEIL((ReqSize+1)/4)	[8]	timeout	timeout error	Footer
5+CEIL((ReqSize+1)/4)	[9]	eofe	End of Frame with Error	Footer
5+CEIL((ReqSize+1)/4)	[10]	frameError	Framing error detected	Footer
5+CEIL((ReqSize+1)/4)	[11]	verMismatch	Version Mismatch Error	Footer
5+CEIL((ReqSize+1)/4)	[12]	reqSizeError	Request Size Error	Footer
5+CEIL((ReqSize+1)/4)	[31:13]	Reserved	Always zeros	Footer

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