Page History

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• Support an AXI4-Lite and AXI4 firmware modules
  • SrpV3AxiLite.vhd will only support 32-bit transactions and 32-bit alignment
  • For applications that need non 32-bit transactions or non 32-bit alignment for AXI-Lite, we can achieve this by bridging the SrpV3Axi.vhd with the AxiToAxiLite.vhd
• Echos back the AXI stream's TDEST
• Header will include:
  • SRP Version number: (8-bits)
    • Always echo backs the local version (0x03)
  • OP-Code: Non-Posted Read, Non-Posted Write, Posted Write, NULL (2-bit)
  • Spare (6-bit)
  • Retry counter (8-bit)
  • Timeout counter (8-bit)
    • In units of 100 ms
    • If 0x0, no time out
  • Transaction ID: (32-bits)
  • Base Address of bursting (64-bits)
  • Request Size  (32-bit)
    • In units of bytes
    • Max. read size is 2³²
    • Max. write size is 2¹²
      
• Header will be echoed except for:
  • SRP Verson number
• Footer will be 32-bit, zero on success, and will include:
  
  • Memory Bus response (8-bit)
    • success == 0x0
    • failed != 0x0
  • Timeout flag (1-bit)
  • Request's EOFE (1-bit)
  • Version Mismatch (1-bit)
  • Invalid request size (1-bit)
  • All other bits must be 0x0

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