Page History

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12:54PM
Extracted thee FEB cold plate and removed all FEBs. The two non-working FEBs (L1t and L6b) were sent to Ben directly; the other were given to Lupe for rework.
The default rework is to add Zener diodes to all FEBs and also to remove the FPGA LED that is always on (it's on the cooling plate side so we can't see it anyway; it indicates FPGA programming OK).
I added the serial number of each board to the mapping on the DAQ & Power Mapping in Group C page.

4.00pm
Found that P5 connector had DIG_GND swapped across the flange. The two pigtail connector seemed ok (the twisted pair went into adjacent pins as expected) which leaves the only possibility of having a swap at the pads on either side of the flange board.
=>Danh Du corrected this on the air side P5 connector.

5.15pm
Placed FEB L1t on cold plate next to the SVT box and connected P1 power cable. Without detector attached the FEB powers up fine with expected currents. When connecting the L1t detectors we see again a 3A current on DIG as before. We also tried connecting L1-3 spare half-modules with the same result. We then swapped out P1 with P5 and powered the FEB as if it was L1b. This was successful. Thus the problem points to some problem in the L1t power cable. Tomorrow we need to ohm out that path to see if we can find a problem.

Equipment

Interlock board

see Group C interlock board for instructions on monitoring and controls.

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