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Feature | Look for |
|---|---|
Architecture | ARMv7-A |
Processor | Cortex-A9, Cortex-A9 MPCore |
Instruction sets | ARM, Thumb, Jazelle, ThumbEE |
Floating point | VFP3-32 |
Vector operations | NEON, Advanced SIMD |
DSP-like ops | EDSP |
Timers | Generic Timer |
Extra security | TrustZone, Security Extension |
Debugging | JTAG, CoreSight |
Multiprocessing | SMP, MPCore, cache coherence, Snooper |
The Cortex family of ARM processors incorporate as standard some features that used to be optional in earlier families and were designated by letters following the family names: (T)humb instruction set, (D)ebugging using JTAG, faster (M)ultiplication instructions, embedded (I)CE trace/debug and (E)xtended instructions allowing interoperation of ARM and Thumb code. Oddly, Cortex processors don't have any integer division instructions. MPCore variants have new synchronization instructions favored over the older Swap (SWP): Load Register Exclusive (LDREX) and Store Register Exclusive (STREX).
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When the MMU is fetching translation table entries it will ignore the L1 cache unless you set some special bits in the Translation Table Base Register telling it that the table is write-back cached. Apparently write-through caching isn't good enough but ignoring the L1 cache in that case is correct, if slow.
Caches
Multiprocessor support
Sharable memory
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Snooper
SMP mode
TLB broadcast mode
System state immediately after a reset
State | ARM | ||
Mode | Supervisor | ||
Privilege level | 1 | ||
Exceptions | All disabled save for Reset | ||
Security level | Secure | ||
Secure mode MMU | Disabled (SCTLR.M == 0) | ||
Nonsecure mode MMU | Random (SCTLR.M random) but not functioning since Secure mode is active | MMUs | Both disabled |
PC | 0x00000000 or 0xFFFF0000 depending on reset behavior of SCTLR.V bit | ||
Caches | All disabled, contents random | ||
Branch tracer (BTAC) | ??? | ||
Snooper | ??? | ||
SMP mode | ??? | ||
TLB broadcast mode | ??? | ||
SP | Random | ||
Other GPRs | Random | ||
CSPR CPSR I-bit | 1 | ||
CSPR CPSR F-bit | 1 |
The MMU's TLB entries have random content so one must at least disable invalidate all TLB entries before enabling the MMU. With the MMU disabled all instruction fetches are assumed to be to Normal memory while data accesses are assumed to be to Ordered memory.
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