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When the MMU is fetching translation table entries it will ignore the L1 cache unless you set some special bits in the Translation Table Base Register telling it that the table is write-back cached. Apparently write-through caching isn't good enough but ignoring the L1 cache in that case is correct, if slow.
Caches
SMP support
System state immediately after a reset
State | ARM |
Mode | Supervisor |
Privilege level | 1 |
Exceptions | All disabled |
| save for Reset |
Security level | Secure |
MMUs | Both disabled |
PC | 0x00000000 |
Caches | All disabled |
SP | Random |
Other GPRs | Random |
CSPR I-bit | 1 |
CSPR F-bit | 1 |
The MMU's TLB entries have random content so one must at least disable all TLB entries before enabling the MMU. With the MMU disabled all instruction fetches are assumed to be to Normal memory while data accesses are assumed to be to Ordered memory.
All cache lines should be invalidated prior to enabling the caches.
The Reset exception is of the highest priority so in effect all others are disabled. Reset itself can never be disabled.
The Reset handler must set the initial SP values for all modes.