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System state after a reset
State | ARM |
Mode | Supervisor |
Privilege level | 1 |
Exceptions | All disabled |
Security level | Secure |
MMUs | Both disabled |
The MMU's TLB entries have random content MMU: disabled with TLB disabled. Contents of TLB entries are random so one must at least disable all TLB entries before enabling the TLBMMU. With the MMU disabled all instruction fetches are assumed to be to Normal memory while data accesses are assumed to be to Ordered memory.
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