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***Note: You will need sudo access to your machine.***
Setup for large file systems on GitHub.
git lfs install
Verify that you have git version 2.13.0 (or later) installed.
git version
Verify that you have git-lfs version 2.1.1 (or later) installed.
git-lfs version
Clone the example repository into the "SNLDemo" directory.
git clone --recursive https://github.com/slaclab/snl-Examples.git SNLDemo
***Note: This repo assumes that you are using the default MLP model. If you are using a different model, make sure you define its structure in all necessary files and follow the instructions in this section.***
In "SNLDemo/firmware/shared/SnlMLP/src/Network.cc," ensure that the model is defined in class Wba - construct(). For example, for this MLP model, the construct method looks like this:
m_layer0.construct (weights.m_layer0); //Dense m_layer1.construct (weights.m_layer1); //Dense m_layer2.construct (weights.m_layer2); //Desne
as there are 3 dense layers.
Add or remove typename from the Wba class as necessary. For this model, it looks like this:
typename Layer::Wba<0> m_layer0; typename Layer::Wba<1> m_layer1; typename Layer::Wba<2> m_layer2;
Set up Xilinx licensing. If you are on the SLAC network:
source SNLDemo/firmware/setup_env_slac.sh
Otherwise, you will have to install Vivado/Vitis and install the Xilinx licensing.
Go to the HLS target directory and build the HSL.
cd SNLDemo/firmware/shared/SnlMLP make clean
Launch the GUI.
make gui
Close the GUI and run the following commands in the terminal. This will generate an IP zip file.
make clean make
After the process finishes, you will see two lines like this.
INFO: [HLS 200-111] Finished Command export_design CPU user time: 18 seconds. CPU system time: 1.15 seconds. Elapsed time: 30.02 seconds; current allocated memory: 13.047 MB. /u1/jaeylee/Projects/SNLDemo/firmware/shared/SnlMLP/ip/SnlMLP-v1.0-20231030114131-jaeylee-46d334d.zip
Copy the part that begins with "/ip/SnlMLP..." to your clipboard. Make sure that the name does not contain "dirty," which means it was made using uncommitted code.
Launch vim to edit the "ruckus.tcl" file under the "SnlMLP" directory.
vim ruckus.tcl
Keep note of the IP name. For example, in this "ruckus.tcl" file
if { [get_ips MLP_50] eq "" } {
The name is "MLP_50."
In "ruckus.tcl," replace the path that begins with "/ip/SnlMLP" with the copied path in your clipboard. Save the modified file.
Now, go to "SNLDemo/firmware/python/snl_MLP/_Application.py" and create the correct variables that correspond to the weights and biases of your model. To get the correct offset and number fields, go to "SNLDemo/firmware/shared/SnlMLP/ip" and unzip the ip zip file by running
unzip [IP_ZIP_FILE].zip
Then, go to "SNLDemo/firmware/shared/SnlMLP/ip/drivers/processStream_v1_0/src" and run
cat xprocessstream_hw.h
The output will show the offset and number for each variable. Create your variables according to these values. *Note: "number" stands for the "DEPTH" values in the output.
Go to
SNLDemo/firmware/targets
and run "ls."
This will output a list of available FPGAs. For example,
shared_version.mk SnlMLPAlveoU200 SnlMLPKcu105 SnlMLPKcu105HlsBypass SnlMLPKcu1500
After you select an FPGA, "cd" into it and run
make clean make
This will take a long time. After it finishes running, run
make gui
This will bring up the Vivado GUI.
Setup the Rogue environment.
cd SNLDemo/software source setup_env_slac.sh
Run the PCIe firmware update script with the path equal to "SNLDemo/firmware/targets/<Name of FPGA>/images"
python scripts/updatePcieFpga.py --path .../SNLDemo/firmware/targets/<Name of FPGA>/images
Reboot the computer.
sudo reboot
Open "software/NoteBook/DataProcessing.ipynb."
After changing the paths to be correct, you will be able to run the cells and get the accuracy of your model compared to the ground truth labels at the end. You will also see a count of all labels your model generated, and you can compare this count to the count you got in "MLP_MNIST_Training.ipynb" from "SNLDemo/firmware/python/snl_MLP" to see if your FPGA output matches your software output.
Note that the predicted class counter for the FPGA output (left) matches the predicted class counter for the software output (right), meaning that the model was successfully moved to the FPGA.