Motivation

Need simple serial interface for configuring registers and sending commands to an ASIC

Must allow for back pressure, so that ASIC can signal that it is done with a command or ready for new data.

Existing Standards not a good fit

SPI: No back pressure. Requires polling.

I2C: Back pressure possible through clock stretching, but complex protocol and implementation.

Difference between SACI Version 1 to Version 2

  • Removed the CMD[6:0] feature from the protocol.
    • Version 2 only supports 32-bit read/write register transactions
  • Increase the ADDR bits from 12-bits to 30-bits to support up to 4GB of memory address space on the ASIC
    • Only ADDR[31:2] are sent because the memory address space is now byte address (instead of word address)
  • Renamed Master/Slave to Coordinator/Subordinate

SACI Features

Coordinator/Subordinate Serial Interface

4 Signals

  • 3 shared: saciClk, saciCmd, saciRsp
  • 1 dedicated select line per slave: saciSelL
  • Allows multiple slaves on same SACI bus. (Similar to  SPI.)

Serial data transmitted on rising edge of clock and sampled on falling edge. MSB first.

Toggling saciSelL resets Slave state machine in case of lockup.

Waveforms

Writes

  • Coordinator lowers saciSelL
  • Coordinator sends Start Bit, Write Bit, Command, Address and Data
  • Subordinate responds with Start Bit, Write bit, Command and Address
  • Coordinator optionally raises saciSelL when done.


Reads

  • Coordinator lowers saciSelL
  • Coordinator sends Start Bit, Read Bit, Command and Address
  • Subordinate responds with Start Bit, Write bit, Command, Address and Data
  • Coordinator optionally raises saciSelL when done.

Contact

Ben Reese

bareese@slac.stanford.edu

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