Layer stackup

With high-speed digital designs the first goal when choosing the layer stackup should be to ensure that each signal layer has a solid ground return plane next to it (ideally above and below). Power planes could be used, but adds the complexity that the whole power distribution network (PDN) must be analyzed to ensure the return paths are localized near the signals, which might require placing additional bypassing capacitors around the board. It is therefore, as a start, easier to use ground planes instead of power planes.

The placement of the signal layers relative to the where the components are (top or bottom) is also important as it can reduce the need for back drilling or the use of blind vias. If the pads of component A and component B are both on the top layer, it would be advantageous to route the signals on an internal layer near the bottom of the stack. This minimizes the via stubs.

Power planes should ideally be placed with a ground plane right next to it to, which creates capacitive coupling between the power and the ground plane and therefore a low impedance path for return currents. This is discussed in the following articles from Altium:

• https://resources.altium.com/p/should-you-use-your-power-plane-as-a-return-path
• https://resources.altium.com/p/board-layer-stackup-considerations-for-high-speed-board-design
• https://resources.altium.com/pcb-layer-stackup

Routing

Routing plays a major role in high-speed digital design and there are several tricks and features that have to be considered to ensure that a communication channel on a PCB works at the wanted frequency. The sections below goes through some key design elements and show how their implementation affects the signal through the use of simulation with Hyperlynx. Note that this is not intended as a guide on how to simulate a PCB with Hyperlynx.

A PCB has been designed in Altium with the intention to showcase these feature and to use with the Hyperlynx simulation, the project can be found on the SLAC Altium 365 project page under the name GT-Readout-Platform-Simulation-Board.

Simulation sanity check

As a sanity check of the simulation setup, two identical signal paths can be simulated, which should give identical result. The only difference between them should be from numerical precision in the simulation.

Plots

HTML report

Complete Hyperlynx HTML report: a0-sanity-check-html-report.zip

Conclusion

The simulation results are identical for both traces as expected.

Removal of non-functional pads

By default in Altium (and Hyperlynx) every via on the board has pads located on every layer, even on layers where the signal is not routed. This can be seen illustrated in the diagram below to the left, where the signal is only located on layer 1 and layer 3. All these extra pieces of metal sticking out from the via changes the impedance of it. We should expect a lower impedance since these extra metal results in a closer proximity to the reference ground metal. By removing these we end up with a via stack as can be seen below on the right. Note that there is still a pad left on the bottom which is usually needed for manufacturing purposes.

Plots

HTML report

Complete Hyperlynx HTML reports:

• a1-with-pads.zip
• a1-without-pads.zip

Conclusion

From the TDR plots above we can see that by removing the non-functional pads the impedance of the vias are more closely matched to target differential impedance of 100 ohm. This results in shifting the resonance dip in the loss plots in frequency domain towards higher frequencies. We can also conclude that by only removing non-functional pads is not enough to achieve a channel with high-bandwidth capabilities, but it is an important step that should be taken moving forward.

The non-functional pads will be removed from all simulations after this one below.

Back drilling of via stubs

The signal vias have been back drilled according to:

• A0: no back drilling
• A1: back drilling on the left side (as shown in All traces below) from the bottom only
• A2: back drilling on both sides (top and bottom)

Plots

HTML report

Complete Hyperlynx HTML report: a2-backdrilling-html-report.zip

Conclusion

Without backdrilling (A0) the signal response of the channel is not good as it creates large impedance mismatch as the signal transitions through the vias. Back drilling (A1) from only one side, assuming that side has the longest via stub, improves the signal response substantially.

Back drilling from top and bottom (A2) could increase the cost of production.

The back drilling done here is ideal, meaning that 0mil of setback (the stub that is left after drilling) is used. In reality this is more in the range of ~5mil with current production technology. The size of the drill can also have an impact since it will affect the amount and type of material that is left between the two signal vias.

The alternative to back drilling is to use blind and/or buried vias, which is a more advanced PCB process. See this article from Altium: https://resources.altium.com/p/how-to-use-blind-and-buried-vias-in-altium-designer

Via stub lengths

In this simulation we are looking at how the stub left over after back drilling affects the signal. A range from 0mil to 70mil stubs are used as can be seen below.

Plots

HTML report

Complete Hyperlynx HTML report: a3-via-stub-length-html-report.zip

Conclusion

As expected, longer stubs results in worse performance. Looking at the Return loss TX side plot we can see that at around 12 GHz we have the following values:

This is roughly a 2 to 3dB increase in the return loss for each 10mil of stub.

The insertion loss starts to suffer at around a 30mil stub (GT3) where a first resonance dip appears at around 38 GHz.

Via antipad

Depending on how the vias are arranged for a differential signal there can be copper left between the two vias that affect the impedance seen by the signal as it transitions through the via. Removing this copper changes the impedance which is what will be shown in this simulation setup. As be seen below, there are 8 differential pairs that terminate in pads on the top layer on the left, transitions down to layer 3, are routed across the board and then transitions down further to the bottom layer. An example of a 25mil antipad is shown in the second screenshot. Note that this antipad in the ground planes is done for all the ground planes that the signal transitions through along the via. The size of the antipad (the width of the line that is used to create it) varies from 0mil to 40mil in 5mil steps. 

Vias on the both sides have been back drilled to ideal conditions (no stub) to reduce the effect of stubs in this simulation.

Plots

HTML report

Complete Hyperlynx HTML report: b-via-antipad-html-report.zip

Conclusion

The "TDR TX side extremes" plot shows that GT_B_P0 (no antipad) has the lowest impedance values in the dips at both ends while GT_B_P7 (40mil antipad) have the highest and GT_B_P4 (25mil antipad) is somewhere in the middle. This can be explained if we consider the impedance of a line in relation to its distance to a reference plane, where the distance between them defines the impedance. A small distance results in a small impedance (GT_B_P0), while a large distance results in a large impedance (GT_B_P7).

Ideally we would want to characterize the via along with the antipad and distance to return vias around it using some sort of 3D field solver. This would make it possible to ensure that the impedance seen by the signal as it transitions through the via is matched with the target impedance (100 ohm differential in this case).

In the frequency domain we can see that the dip in the return loss RX side shifts to higher frequencies as the antipad size is increased. From the TDR plots we expect that the 25mil antipad size (GT_B_P4) to be the "most matched" impedance-wise. Looking at the return loss TX side we can see that there is a turning-point around GT_B_P4 where the larger antipad size after results in a worse return loss.

AC coupling capacitors - top vs bottom

If there are AC coupling capacitors used in the path of the signal there are two options for their placement; top or bottom side of the board. Which one is better? In this simulation setup the signal is routed on layer 3 and transitions to the top or bottom layer where the AC coupling capacitors are located as shown below. The signal is therefore closest to the top layer. Another configuration could have the signal routed closer to the bottom layer.

In the simulated configuration, the signal does not change reference plane as it transitions from layer 3 to the top layer, while the transition to the bottom layer does change the reference plane.

The following signals are used in the simulation:

• GT_CX_P1: AC coupling capacitors are mounted on the bottom layer
• GT_CX_P3: AC coupling capacitors are mounted on the top layer

Plots

HTML report

Complete Hyperlynx HTML report: c0-ac-capacitors-top-vs-bottom-html-report.zip

Conclusion

TODO

Trace shape

Altium supports routing traces in many different shapes (see https://www.altium.com/documentation/altium-designer/interactive-routing-pcb#controlling-the-corner-style). This simulation example tries to explore if the style of the routing has any impact on the high-speed performance of the trace. The following four test cases are used:

• D0: Straight, for reference.
• D1: Round with 45 degree transitions
• D2: Round with 90 degree transitions
• D3: 45 degree angles

Plots

HTML report

Complete Hyperlynx HTML report: d-trace-shape-html-report.zip

Conclusion

D2 is clearly the worst performant routing with large impedance variation throughout the whole length of the trace. The difference between the rounded 45 degree (D1) and the sharper one (D3) seems to be too small to see in this simulation setup.

In Altium it is easier to route using the 45 degree (D3) since it supports just dragging the traces around while keeping the differential gap between the pairs. This does not work for the rounded 45 degree which would require re-routing the traces if they have to be removed.

Routing layer

This simulation example is to explore how the signal is affected by which layer it is routed on. The example has 18 layers in total, with 5 internal signal layers. With this stackup, the traces on the top and bottom layer are wider (6mil width / 4mil gap) compared to the internal layers (3.5mil width / 4mil gap) for 100 ohm impedance matched differential pairs. If all components are located on the same side of the board it might be tempting to route exclusively on external layers to avoid via transitions, but it's important to understand how this affects the signal as this simulation example will do.

The following signal traces have been laid out on the PCB below:

Plots

HTML report

Complete Hyperlynx HTML report: e-different-layers-html-report.zip

Conclusion

There is a clear difference between routing on internal versus external layers. There is ~2dB more insertion loss on external layers at around 12 GHz, which increases to ~4.5dB at 24 GHz. The return loss has a more gradual slope for the external layers compared to the internal.

The TDR for the internal layers show a shift in time from E1 to E5, which is expected due to the longer path length through the vias as we go further down into the layer stack. There also seems to be a smaller variation in the impedance mismatch for the layers closer to the top, which could be due to the signal spending less time in the via where the impedance mismatch is along the signal path. If the via transition is constructed with a better matching to the 100 ohm differential impedance, this result could be different.

The TDR for E0 and E7, where the signal is only on the top and bottom respectively, are identical as expected.

Another interesting observation is to compare the TDR of for example E0/E7 and E1, where the E0/E7 plots are "shorter" in time. This is due to the shorter trace path for E0/E7, since it doesn't go through a via, but also due to the slightly faster signal propagation on the external layers. The same result can be seen for E6, which transitions through vias but is routed on external layers.

Resources

• https://www.protoexpress.com/blog/best-high-speed-pcb-routing-practices/
• https://www.ti.com/jp/lit/an/slla414/slla414.pdf
• https://resources.altium.com/p/how-design-high-speed-rf-transitions
• https://resources.altium.com/p/everything-you-need-know-about-stitching-vias
• https://docs.amd.com/r/en-US/ug583-ultrascale-pcb-design/Differential-Vias
• https://www.sigcon.com/Pubs/HSDDsem.html