Overview
This module draws inspiration from the AxiStream Batcher Protocol Version 1, which uses the AxiStreamBatcherEventBuilder.vhd. Unlike the original design, which creates a single super-frame per event, this module transmits event frames in a guaranteed sequence. As a result, each event consists of multiple frames, but the order of these frames within an event is always preserved.
In the AxiStreamBatcherEventBuilder.vhd, a super-header and multiple sub-frame tails are prepended or appended to the stream. In contrast, this module eliminates tail appending and instead prepends a header to each frame as it is forwarded through the sequencer. This header includes all the metadata necessary to reconstruct AXI stream sideband information on the receiver side, such as TDEST, TUSER_FIRST, and other relevant signals.
Requirements on the AXI Stream Configuration
- AXIS_CONFIG_G.TDATA_BYTES_C must be a power of 2
- AXIS_CONFIG_G.TDATA_BYTES_C must be greater than or equal to 8 bytes (64-bit)
- This is because the header is 64-bits
EventFrameSequencerMux Details
Firmware Generics
| Name | Description |
|---|---|
| NUM_SLAVES_G | Default: 2 Number of Inbound AXIS streams |
| MODE_G | Default: "INDEXED" In INDEXED mode, the output TDEST is set based on the selected slave index In ROUTED mode, TDEST is set according to the TDEST_ROUTES_G table |
| TDEST_ROUTES_G | Default: Slv8Array := (0 => "--------") In ROUTED mode, an array mapping how TDEST should be assigned for each slave port Each TDEST bit can be set to '0', '1' or '-' for passthrough from slave TDEST. |
| TDEST_LOW_G | Default: 0 In MODE_G="INDEXED" mode, assign slave index to TDEST at this bit offset |
| TRANS_TDEST_G | Default: x"FF" Set the TDEST to detect for transition frame |
| AXIS_CONFIG_G | Defines the AXI stream configuration and used to determine the AXI stream width from AXI_CONFIG_G.TDATA_BYTES_C |
| INPUT_PIPE_STAGES_G | Default: 0 Set to 1 to register the flow control on the intput streams to help with making timing |
| OUTPUT_PIPE_STAGES_G | Default: 0 Set to 1 to register the flow control on the output stream to help with making timing |
EventFrameSequencerDemux Details
Firmware Generics
| Name | Description |
|---|---|
| NUM_MASTERS_G | Default: 2 Number of outbound AXIS streams |
| AXIS_CONFIG_G | Defines the AXI stream configuration and used to determine the AXI stream width from AXI_CONFIG_G.TDATA_BYTES_C |
| INPUT_PIPE_STAGES_G | Default: 0 Set to 1 to register the flow control on the intput streams to help with making timing |
| OUTPUT_PIPE_STAGES_G | Default: 0 Set to 1 to register the flow control on the output stream to help with making timing |
EventFrameSequencer Header Details
Header Description
| Bits | Name | Description |
|---|---|---|
| 3:0 | VERSION | Version info. Should always be 0x1 |
| 7:4 | WIDTH | log2(AXIS_CONFIG_G.TDATA_BYTES_C)
|
| 15:8 | SEQ | Packet sequence number of event |
| 23:16 | TUSER_FIRST | First byte of the TUSER field |
| 31:24 | TDEST | Transaction destination field |
| 39:32 | NUM_STREAMS | Number of streams |
| 47:40 | index | MUX Index |
| 55:48 | frameCnt | Event frame count (zero inclusive) |
| 63:56 | numFrames | Event frame Size (zero inclusive) |
Overview
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