-------------------------------------------------------------------------------
-- Title         : Version Constant File
-- Project       : CSPAD 140k  C02, Analog C03, ASIC V1.5
-------------------------------------------------------------------------------
-- File          : Version.vhd
-- Author        : Ryan Herbst, rherbst@slac.stanford.edu
-- Author        : Sven Herrmann, herrmann@slac.stanford.edu
-- Created       : 03/18/2012
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-- Description:
-- Version Constant Module
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-- Copyright (c) 2012 by SLAC. All rights reserved.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

package Version is

constant FpgaVersion : std_logic_vector(31 downto 0) := x"140B0324"; -- MAKE_VERSION

end Version;


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-- Revision History:
-- 05/06/2011 (0xCAFF0001): Initial Version
-- 07/25/2011 (0xCAFF0002): Fixed digital pot mapping.
-- 08/08/2011 (0xCAFF0005): Changed data format;
-- 08/08/2011 (0xCAFF0006): Changed data format;
-- 08/08/2011 (0xCAFF0007): Changed data format;
-- 08/08/2011 (0xCAFF0008): Added DAC control.
-- 09/28/2011 (0xCAFF000A): Added internal rate gen and pulse output.
-- 09/30/2011 (0xCAFF000B): Added force amp reset and adc period adjust.
-- 10/20/2011 (0xCAFF000C): Added adjustable ADC counter.
-- 01/26/2012 (0xCAFF0020): New pot shift map for updated analog board.
-- 01/26/2012 (0xCAFF0021): Fixed.
-- 02/12/2012 (0xCAFF0022): Temp version with comp bias always enabled.
-- 02/13/2012 (0xCAFF0023): Iss2 now timed with iss5.
-- 02/15/2012 (0xCAFF0024): All bias values now times with iss5
-- 02/15/2012 (0xCAFF0025): Added debug.
-- 02/15/2012 (0xCAFF00E0): Integrated Sven's changes.
-- 09/30/2012 (0xCAFF00E1): synchrotron optimised integration time included
-- 10/16/2012 (0xCAFF00E2): changed bootup reset generation
-- 11/19/2012 (0x140B0303): conditional generate for analog PCB C02 and C03
-- 01/18/2013 (0x140B0308): intDelay (RUN trigger) and extDelay (DAQ trigger)
-- 01/18/2013 (0x140B0309): fixes
-- 01/31/2013 (0x140B0310): power configuration register
-- 03/07/2013 (0x140B0312): disabled the zero shifting into the mem shift register
-- 03/07/2013 (0x140B0313): puts out triggers at the MPS output (for Jack)
-- 06/25/2013 (0x140B0314): put 2 ASIC temps into the data stream
-- 07/10/2013 (0x140B0315): ADC clock generator with set and hold time
-- 01/23/2013 (0x14152001): New build structure with common code
-- 10/01/2013 (0x14152002): fixed couple bugs
-- 11/11/2013 (0x140B0320): changed version numbering back to established scheme
-- 11/26/2013 (0x140B0321): fixed the run/daq trigger assignment
-- 06/04/2014 (0x140B0322): mpsOut shows PRST for FEL timing
-- 07/22/2014 (0x140B0323): removed all reset from TEC_CNTRL and changed ST_CLK_SET state to support minimum state length of 1 clock cycle (0 counts)
-- 07/30/2014 (0x140B0323): pipelined the shiftSelect logic, so the first 96 channels use one delay (shiftSelectA) and the rest uses +1 (shiftSelect+1)
-- 08/30/2014 (0x140B0323): COL&ROW clock duty cycle control: clkPeriod(1 downto 0) for low state (hold), clkPeriod(3 downto 2) for clock high state (setup)
-- 08/30/2014 (0x140B0324): compiled one version with 104MHz instead of 125MHz
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