SuperCDMS:

Intro files

• Richard overview talk pdf ppt
•  Pelle's tower wiring and electronics talk: ppt pdf
•  Bruce Hines' readout electronics talk:  ppt pdf
• TDR pdf

L3 Manager for Tower Wiring and Electronics

L2 is Richard Partridge
L3 deputy is Martin Huber, Colorado University (in charge of SQUID fabrication)

• Budget and schedule responsibility and weekly reports to CAM (Richard P. at SLAC) Here is P6 pdf
• Coordinate fabrication, testing, interfaces with other subsystems
• Coordinate tower electronics background contribution
• SQUID fabrication coordination

Electronic design

• Design development, schematic and layout for very custom PCB taylored for tower testing  in close collaboration with Richard, etc. Expect there will be 2 or 3 PCBs in the next 6 months. (March to September 2018)
• Work closely with the mechanical engineers for interfaces
• Need to support and work closely with the layout group, and in cases w/o their help, in cases were specific fab is needed for radiopure experiments like this
• Working closely with vendor to produce superconducting flex cables

Electronics general support

• Design development, schematic and layout for PCBs taylored for tower testing in close collaboration with SuperCDMS collaborators
• PCB schematic and layout for testing on both normal tools (dxDesigner, PADS, GC-Prevue/CAD) and express PCB.
• Coordinate testing of tower wiring and electronics PCBs and flexible PCBs: writing testing instructions, documentation,
• Specific support: analog pre-amp design/fab, rf filter procurements, evaluation and testing
  • Support testing of analog electronics in the clean room: using spectrum analyzer to measure noise perf., design, use simple custom pre-amps, characterize RF filter performance, help with noise models, etc.
• Help support noise calculation: both spice simulation and manual calculation of transistor level noise models

• First tower integration: help design and testing of mechanical support structure for PCB integration on tower(this is done with Marco and other mech. eng.)

• Coordinate and oversee testing of transistor testing at Caltech and the subsequent loading of transistors with vendors to mezzanine boards for use in the experiment

L3 manager for Readout Cables for SuperCDMS

• Budget and schedule responsibility and weekly reports to CAM (B. Hines, Denver) Here is P6 pdf
• Coordinate assembly and testing of more test cables (we have the hardware) with electrical shop and CDMS folks.
• Coordinate assembly and testing of first long readout cables
• Coordinate interfaces and adjust designs based on interactions with other subgroups in the project: cryogenics, readout electronics and tower.
• Help with overall electrical design; transmission line simulation
• Responsible for eTraveler and radiopurity control
• Fabrication/Vendor contacts for hardware procurement of the wire, PCBs and assembly
• Work closely with and supervise assembly in electronics shop

Outstanding tasks and detailed documentation

See: SuperCDMS Task Transition

FY19 best guess:

• The above support for testing and tower assembly in the clean room continues.
• Likely the pure design of PCBs and circuitry will become small.
• L3 manager items continues. 
• Coordination of radiopurity assays will continue
• Coordination of fabrication for production (this should only be small adjustments to designs)
• Readout cable duties will be mostly about finding a vendor that can build many of them and testing that procurement and coordinating with L2 manager and Fermilab cryogenics engineers on mechanical interfaces.

Dune related

 LAr TPC physics requirements

• Past tasks. Completed and if so where are files?

  • Involved in flow-down to cold electronics; calculations and back of the envelope estimates requirements

  • Reading, commenting and supporting  documentation for DUNE proposals from the SLAC group

Lead and coordinate testing development at SLAC for the CRYO ASIC

• Completed? Files? DUNE Readout Cabling Testing; coordinating with consortium leaders on testing (incl. procurement and such)
• Completed? Files? Defining ASIC testing requirements; working closely with the ASIC group (Angelo, Aldo, Faisal) to figure out what they need in terms of interfaces and signaling
• Completed? Files? Electronic circuit design; estimate and calculate circuit properties relevant for the ASIC interfaces (ADC speed, resolution, noise, filtering)
• Completed? Files? Thermal performance and mechanical compatibility; power estimations for power and thermal compatibility for testing cryogenically, working with tech's to build test hardware (dewars, flanges, etc.)
• Lead design of initial testing of the ASIC and coordinate closely with ASIC group and DUNE collaborators for requirements
• Plan procurement, assembly and checkout of hardware for testing setups
• Do estimate calculations for both electrical and thermal performance of the test setup
• Coordinate with other institutions on testing: hardware availability
• Coordinate with EE for getting support for the ASIC in terms of firmware and software (probably Dionisio)
• Analysis software and debugging of ASIC together with the ASIC group

PCB schematic and layout

• Design and layout of multiple PCBs (some for cryostat operation, ASIC carrier board, epix interface boards, high-speed and HV cryostat penetration board)
  • the schematics will be mostly done before P leaves 
  • and need to be taken over by somebody: coordination, layout, fab, testing

FY19 best guess:

• The above mostly continues for DUNE
•  Lead overall design of testing ASIC beyond single chip: research and design requirements for the readout systems together with EE, Ryan, etc. (e.g. changes/updates needed for RCE system)
•  Play a role in the analysis of testing data and software for that.
•  Support testing efforts at other institutions (Hawaii, etc)

HPS related

• At some point we need to get back into testing the full DAQ and perhaps implementing the ideas Ben and P. have had for calibration and data taking stability. I think this will happen a few months before the next run so in the fall/end of 2018 or so.