Hybrid

It seems that the biasing filtering for the detector still needs to be defined. In particular, the multistage filter uses 100V caps (we need at least 500V), 100uF capacitances (unrealistically large) and no resistances. In the past we have used 1K resistors and the largest surface mount capacitances we can get in the voltages we need. Looking at what AVX and Johanson have, it looks like 220 or 470 nF at 500V or more are the best we can do (and probably just fine).

An issue here is the drivers for transmitting data between the hybrid and the RTM: we need to make sure they are capable of driving those lines. In order to do that, we need to specify the length of cable that will be needed to connect the two. This depends upon the location of the DAQ and the cable routing that will be used. How long can those lines be as designed?

Comments and Questions from SCIPP: 

1. In the bias filter circuit, there should be another resistor on the BIAS RET line between C22 and C23. Note: ATLAS currently uses 5.1 k for R26 and R27 and 1k for the added resistor on the return line. Furthermore, ATLAS uses 10 nF capacitors for C22, C23 and C24.
2. There needs to be an AC tie between the sensor BIAS RET line and the V1_25 node on the hybrid. It looks like ATLAS has a DC tie, but it is not operating the readout chip with an offset small signal common. So what size capacitor should this be?
3. There should also be an AC tie between the sensor BIAS IN and V1_25. What should the size of the capacitor be?
4. The Mechanical and Cooling Spec sheet states that “Conductive supports shall have impedance connection to AVDD.” Why to AVDD and not V1_25? Is this because of the way the front transistor references?
5. The Mechanical and Cooling Spec sheet states that “Bias voltage shall be supplied to the backside directly by wire bonds.” It's unclear if this is wire bonds from Kapton tape to the backside or wire bonds from hybrid to Kapton tape. Wire bonds directly on the backside will need to be protected.
6. During our phone discussion, Tim said that the power supplies available for the test run can only get up to 500 V. This was the reasoning for spec'ing the capacitors and isolation of the sensor backside from its conductive support to only 1 kV. If the cost increase is minimal and the size of the components is not a problem, it would be beneficial to increase both of these specs to 2 kV even for the test run. This will allow for testing of these units on the bench or possibly a test beam at SLAC up to the anticipated max voltage for the full experiment, i.e. 1 kV, after the Test run has taken place. It may be useful to have modules available for such tests while the upgrades to the Jlab beam line are completed.
7. It was surprising to find that the conductive support is referenced to AVDD. Is there a reason for this? If indeed AVDD is the input transistor's reference, then the sensor's ground and AVDD need to be AC-coupled well.
8. What is the reasoning behind encapsulating the wire bonds? They can take some amount of shaking e.g. during ATLAS construction, uncapsulated modules were shipped all over the world. In space applications, it is unnecessary to encapsulate, however, GLAST initially experienced some problems with encapsulation due to the presence of silicone-based material. Is there an experience using Sylgard 186 on wire bonds?
9. At the risk of stating the obvious, it would be good to have a mechanical “handle” and other “touchable” points of support for the modules (While manipulating a module using vacuum suction to the sensor's surface is possible, it is inconvenient).
10. If indeed the sensors need to be flat to 50 microns, we may need to check that they perform well after being flat for a long time. One can have problems with flattening large-area sensors.

More Comments from SCIPP:

11. Sensor supports and nearby conductors:

Conductive sensor frame and support members should not have unnecessarily close proximity to the strips to limit capacitance to EMI carrying objects. The close conductive frame members for a sensor or sensor stack should have common bonding ties to each other, and be isolated as a group from the main cabinet and frame. A single bond tie, low AC impedance @ 20 MHz, should bond at the Analog 1.25 V supply at the rear edge or at the power entry to the PCB.

12. Analog power necking:

The ADA4938 diff amp allows an analog power plane neck strategy. The 1.25 V referencing plane for the group of APVs servicing one sensor can have a single point tie to the rest of the PCB circuit nodes. The ADA4938 should rest in this front power plane, since its drivers exactly balance their differential drive current, and should disturb the power plane minimally.

13. Front power plane with power islands:

For the demanding mixed signal challenge of sensor strips, a  single power plane with power island strategy works well. The power plane should be the Analog 1.25 V supply, since the front transistors reference here, and this will avoid referencing through capacitors. The internal PCB plane should be 2 ounce copper uncut across the group of APVs to a sensor. The two other power sources, 0 V and 2.5 V, should be drawn as "islands", that is, a power plane in the area of a chip to tie the bypass cap and the IC pad together, but the local island serviced by an inductive trace. The trace should be sized to carry the servicing currents, but need be no larger. In series with the power trace, provision should be made for a jumper or air-core inductor. The goal is to force AC currents between chips into a single plane, so that the currents balance locally, and have less EMI.

The "ground pour" layout tool needs to be used carefully. Ground pour could used in the area of a power island, but the island needs to stay contained from jumping the island border. the intention is that currents between islands flow only in the A_1.25 plane.

The 3 analog power connections to the APV sensor group should be single point and grouped together in the PCB layout. The ADA4938 power should also be single point in the same area. A series jumper would be useful here on each supply.  

14. Sensor backplane referencing path:

The sensor backplane tie to the PCB A_1.25 plane should be near the front APV area. The tie needs to be low impedance @ 20 MHz. This excludes simple wires or narrow traces as the bond technique.

Ryan... can we add temperature measurement on the hybrids? I'm a bit concerned that we need to keep track of chip temperatures as part of our conditions data.