• Created by Unknown User (phansson), last modified on Jul 13, 2013
SVT DAQ meeting agenda

Discussion points:

  •  Test SVT result from group C operation (Omar)
  • Plans for July-August:
    • FE board
      • Identify magnetic field compatible components (power, FPGA)
      • Connecterization settled
      • Finish schematic
      • Layout bottleneck?
      • Magnet for testing available at SLAC (mid-Aug and forward should be ok)
      • Target date having prototype
    • Hybrid
      • Schematic
      • Layout?
      • Target date for prototype
        • Constraint: hybrid assembly between Aug-Feb, L4-6 mechanical design starts *now*
        • Need 2 weeks for assembly, wirebonding and testing prototype
        • Time from purchase order to receiving batch
  • AOB

 For those not at SLAC, webex details at: https://confluence.slac.stanford.edu/display/hpsg/Webex+connection+details

Minutes 7/12/2013

Minutes

SVT testing:
Omar looking at some of the runs taken with the SVT and comparing it to what we had during the test run. So far he has had some problems getting good data. It could be related to running at too high rate (1kHz) causing it to drop frames. He'll continue to look into this next week.

Cold testing of modules:
Omar looked a little more carefully at the baseline runs at various temperatures (half module 14). He observed the pedestal drop by about 20 ADC across all chips between room temperature and hybrid temperature of ~3C. The noise was unchanged. There were some interesting features: the most prominent was that the apv25 chip edges was performing gradually worse (they are already a little worse than a normal channel) with lower temperature. It was discussed that the reason for his is that the first channel readout is more sensitive to impedence mismatch that could be caused by temperature changes. We should keep an eye on this as we need to go more than 10C lower and it can potentially become a real problem.

Omar will talk to Ben next week when he's at SLAC to see if we can use the latest dev board.

New hybrids:
We would like to get new hybrids as soon as possible:
Tim will work with Forest on the physical outline of the hybrid next week (before Forest leaves for CERN).
The schematics are pretty much finished (1 day).
Layout is a week but due to bottleneck at SLAC we can't expect to have that quick turn-around time.
Realistically we will target to order hybrids Aug. 15th to get them Sep 1st. This is a few weeks behind official schedule but still ok.
To facilitate this date we decided to have a hybrid design review 26th July. Tim will invite and coordinate with Ryan.

Tim mentioned that we need to make sure that we have pads on the hybrid to enable testing without soldering a flex cable to it. Ryan said that the pads will be large enough to solder (small) twisted pairs for initial testing.

Tim also reminded us that he needs Tung for layout work on the support on the same time scale.

The order for 240 APV25 chips (plenty of spares for prototyping) is in the hands of the business people. The price is down to 15$/chip and Tim expects we'll have them in a ~month (12th Aug).

FE board:
Firmware mostly done.
Schematics done with approximately 1 week of work.
Some more thought has gone into the B-field compatibility and Ryan is in contact with Xilinx. We decided that instead of spinning a board as we want it designed now and test it, we'll use similar boards being produced for other experiments to test and qualify components individually. The FPGA can be tested by ordering an extra board built for DarkSide and the power components can be tested separately. This will probably limit the risk and potentially save money. These boards are being produced now and we plan to test these in mid-August when we get access to the large magnet at SLAC. Pelle will make sure that we have that magnet available for the tests and Ben and Ryan will look into what necessary changes are needed to these boards and order for HPS.

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