• Created by Unknown User (phansson), last modified on Feb 04, 2014

Webex meeting for those not at SLAC: https://confluence.slac.stanford.edu/display/hpsg/Webex+connection+details

Agenda
  • FE board order update
  • Hybrid order update
  • Signal flange board
  • Sub-projects (link)
  • LV power cables (updated estimates)
  • AOB

 

Minutes

Hybrid

PCB should arrive during week 2/3/2014. Since crew at UCSC are away that week we should aim to have them loaded and available at UCSC Monday Feb. 10th for chip bonding. 

FE board

We are expecting to have FE boards arrive at SLAC this week (2/3/2014) and then be sent off for loading. 

Tim was worrying a little about how to strain relieve the connectors on the FE boards. There are no holes available and really no space on the face of the cooling block around the FE boards. 

Cables for testing FE board

LV power to the FE board:
Ryan suggested to solder power directly to the board for the initial tests.  

Connecting four hybrids to FE board: 
We want this approx. 1 week after having started testing the FE board.
 

Opt.1 was to build a test flex cable that is very close to the production version. This allows us to test the basic functionality of the flex design. Would be as short as possible to minimize cost. Ryan mentioned that we do not have this in the budget and we might get stuck in the layout queue waiting causing this to take longer time than we want. 

Opt. 2 is to build a simple PCB with the mating high density connector on one side and a "fan out" into four DB44 connectors. This way we can use the devboard cables and adapter boards to connect four hybrids directly for testing. This should be the cheapest and fastest solution. Preferred by Ryan. This board can have separate HV pins to bypass the need to bring HV through the FE board. This can be done through PCB express. Ben would look into this when he gets back on Wed.

HV to the hybrids:
Ryan suggested that  HV pins can be added to the PCB in Opt. 2 above to bypass the FE board HV connector.

APV25 damage testing

Vitaliy reported that they have injected about 80nC with a 0.5ns rise time and approximately 160mA into a single channel of the APV25. Still no sign of damage. Vitaliy wants to switch to a smaller capacitor and also try another channel to be sure. If no effect is observed the next thing to look into is if it's a chip wide problem and thus we need to pulse a large number of channels across the chip.

 

 

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