From meeting with Matt on Feb. 6 2019

use an mmcm
drive xpmsim
matt/larry eventheadercache takes data/datak and spits out axi

clock domains:
- should use xpmsim l2si-core
- cross axil bus (axilite asynch)
- cross individual registers, use a synch module
- matt will cross boundaries in eventheadercache

**********************************************************************

l2si core package
xpmpackage.vhd

https://github.com/slaclab/l2si-core/blob/master/base/rtl/XpmPkg.vhd

XpmPartitionMsgType

https://github.com/slaclab/lcls-timing-core/blob/master/LCLS-II/core/rtl/TimingPkg.vhd

TimingMsgType

TimingSerializer
- serializes into a 16-bit stream like MGT/GTX
- TP Serializer (timing pattern)
- XPM Serializer (adds readout groups)

Matt and Larry working on EventHeaderCache.vhd (in the github l2si github package)

https://github.com/slaclab/l2si-core/blob/master/base/rtl/EventHeaderCache.vhd

digitizer testbench makes simulated timing signals (l2si/firmware/targets):
pslab01:/u1/weaver/l2si
- might be complicated (many registers for everything the xpm can do)

the xpmsim module might be everything we need, if we can make it synthesize:
https://github.com/slaclab/l2si/blob/28c48f4937cd9e793f34b615a4d6c036658d503e/firmware/targets/hsd_dualv2_sim/hdl/hsd_dualv2_sim.vhd

reduce the number of params (trying to reproduce every xpm features)

this would go to the EventHeaderCache.vhd

paddr: can be anything (
8 readout groups
48-bits per readout group
- trigger bits l0 5 bits, l1 5 bits
- transition bit
- evt counter
- payload (9 bits) used for env

  • No labels