Todo List

Firmware

Task	Description	Status	Date	Owner
AxiLiteCrossbar	Create a xbar for the ASICTOP module	done		Dawood
Port ASIC control module	use Register control as copy and paste into the new module	done		Dawood
Port trigger module	copy from epix-hr-single-10k	done		Dawood
Simulate	Simulate both modules	done		Dawood
axilite address space	Define address space for the ASIC top	started		Dawood
axiStreamRepeaters	Repeaters for the timing information (x5)	Done	15 Nov 2022	Dawood
axiStreamBatcher	Creates the data package with image and timing info (x5)	Done	15 Nov 2022	Dawood
DigitalAsicStreamV2	Port to 2m and increase number of ASICs to 4	Done	15 Nov 2022	Dawood
Synthesis	Make sure design synthesizes completed, update constraints if needed.	Done	15 Nov 2022	Dawood
Software	Complete companion device/register definition, if missing.	Done	15 Nov 2022	Dawood
Hardware deployment	Test HW/SW register access			Dawood/Dionisio
ASIC Model	Port from simulation test bench an ASIC model to a new HDL entity that will mimic the ASIC data path. Needs a data length counter to send one frame per SRO. Map all IO to the ASIC even though some will not be used for this simulation.
DigitalAsicSttreamV3	Create internal module to de-interleave the images			Dawood

Software

Task	Description	Owner
top level structure	Create top level	Dionisio
Add devices ASIC control and trigger	Copy from epix-hr-single-10k, add new addresses	Dawood
Viewer	Discuss with Ben to find out if we should use the new ePix viewr	Dawood/Ben

Test setup

Task	Description	Status	Owner

FW/SW data verification	Fake data generation and display
Check waveforms in HW	Using TTL outputs
Check SACI waveforms	Using analog test points
Check power enable	Using test points or analog board
Check timing receiver	Use timing board from Matt

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