Word# | BITS | Name | Description | Note |
---|---|---|---|---|
0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
1 | [29:0] | Address[31:2] | Start Address | Always 32-bit aligned |
1 | [31:30] | OP-Code | Operation Code | 0x0=Read, 0x1=Write,
|
2 | [31:0] | WriteData[31:0] or ReadCount[8:0] | First Write or Read request counter | Up to 2^9 words per transactions |
... | ... | ... | ... | |
N-1 | [31:0] | WriteData[31:0] | Last Write | |
N | [31:0] | Don't Care | Don't Care |
Word# | BITS | Name | Description | Note |
---|---|---|---|---|
0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
1 | [29:0] | Address[31:2] | Start Address | Always 32-bit aligned |
1 | [31:30] | OP-Code | Operation Code | 0x0=Read, 0x1=Write,
|
2 | [31:0] | WriteData[31:0] or ReadData[31:0] | First Write or First Read | |
... | ... | ... | ... | |
N-1 | [31:0] | WriteData[31:0] or ReadData[31:0] | Last Write or Last Read | |
N | [0] | Fail Flag | Register transaction Error | (response data) |
N | [1] | Timeout Flag | Timeout Error | (response data) |
N | [31:2] | Reserved | Reserved (0x0) | Reserved for Future Use |
Note: "set" and "clear" were defined but never implemented in the software and firmware.