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This manual serves as an end-user manual to configure and use the DaqMux in software. 

Overview

The DaqMux system is shown in Figure 1. The DaqMux component of the FPGA in the application board of the ATCA allows the user to choose to stream up to four streams to the software (IOC) of the input streams routed to the DaqMux. All ATCA projects are configured to have two DaqMuxes, one associated with each AMC daughter board, summing a total of 8 streams routed to software. Each of the two DaqMux has 20 streams of data routed to its input. Acquisition can be either continuous, single, or single many times. In all three cases a trigger is needed. In the continuous case (i.e. continuous mode), at every trigger, the DaqMux acquires a number of configured bytes (i.e. Frame count) and sends them up to software. In single acquisition (trigger mode), the DaqMux is armed only once, and a number of configured bytes (i.e. Frame count) is sent to software with or without a header. Single many times acquisition is just a sub-case of single acquisitions, however; auto re-arm is enabled, and everytime there is a trigger a number of configured bytes (i.e. Frame count) is sent to software with or without a header.

The DaqMux functionality can be summarized as follows:

  • Multiplex up to 4 streams and send forward (to software)
  • Streams can be acquired continuously every time a trigger arrives in continuous mode, or only once upon trigger with or without header (meta data) in trigger mode, or many times with or without header (meta data) in trigger mode when auto re-arm is enabled
  • Possibility of cascading trigger of DaqMux blocks
  • Pause streaming by not overwriting buffers (freeze functionality), therefore nothing is forwarded to software
  • Down sampling and averaging


Figure 1: DaqMux connectivity overview


DaqMux screens

The Graphical user interface of a DaqMux is shown in Figure 2. The main graphical user interface for configuring the DaqMux is quite simple and masks a lot of the DaqMux configurations. It only allows the user to perform the following

  • Choose the source of each of the 4 streams of each DaqMux
  • Stimulate a software trigger in any of the two DaqMuxes (in case trigger mode is chosen)
  • Open complete DaqMux settings
  • View the AMC Up Converter and Down Converter card front panel image


Figure 2: DaqMux graphical user interface


Clicking on the Down Converter Front Panel Image and the Up Converter Front Panel Image shows the up converters and the down converters AMC card front panel images respectively, and are shown in Figure 3. Each port on the AMC card front panel has a name and may be referenced in the DaqMux output stream selection drop box. 

Figure 3: Up and down converter AMC cards front panel images


The DaqMux output stream selection dropbox example is shown in Figure 4.

Figure 4: DaqMux output stream selection dropbox for Down converter (Left) and Up converter (Right)

                   


The syntax used in the DaqMux output stream selection dropbox is one of the following options:

  • 3 parts →  X : Y : Z
    1. X: DaqMux input number
    2. Y: Source of the DaqMux stream
    3. Z: ADC/DAC where that source is connected - intermediate path (Not really important for end users)
  • 2 parts → X : Y
    1. X: DaqMux input number
    2. Y: It can be 
      1. a source generated from
        1. the application side (i.e. DBG/Debug, Test)
        2. Unused DAC/ADC port
      2. Disabled
      3. Test (Simple counter data)

All possible options of the DaqMux input and their descriptions are summarized in Table 1.

Table 1: Possible combinations in the stream channel selection drop down combo box

SourceDescription
${MuxIn#} : TestTest pattern stream (simple counter data)
${MuxIn#} : DisableDisable stream
${MuxIn#} : ADC${ADC#}ADC Source not connected
${MuxIn#} : DAC${DAC#}DAC Destination not connected
${MuxIn#} : DBG${DBG#}Debug streams - application specific and used for debugging (e.g. not used in GMD firmware)
${MuxIn#} : RF IN ${RF#} : ADC${ADC#} FPStream data coming through AMC front panel physical port RF IN ${RF#} through ADC${ADC#}
${MuxIn#} : RF OUT MON : ADC${ADC#} FPStream data coming through AMC front panel physical port RF OUT MON through ADC${ADC#}
${MuxIn#} : DC IN ${DC#} : ADC${ADC#} FPStream data coming through AMC front panel physical port DC IN ${DC#} through ADC${ADC#}
${MuxIn#} : TRIG MON : ADC${ADC#} (FP)Stream data coming through AMC front panel physical port TRIG MON through ADC${ADC#}
${MuxIn#} : CLK PLL DAC : DAC${DAC#}Stream the applied voltage to the voltage controlled oscillator transmitted through DAC${DAC#}
${MuxIn#} : LO PLL DAC : DAC${DAC#}Stream the applied LO signal mixed with RF sinal to get an IF signal transmitted through DAC${DAC#}. This is specific to the LLRF applcation
${MuxIn#} : DAC OUT : DAC${DAC#} (FP)Stream data coming out through AMC front panel physical port DAC OUT through DAC${DAC#}
${MuxIn#} : RF OUT : DAC${DAC#} (FP)Stream data coming out through AMC front panel physical port RF OUT through DAC${DAC#}


DaqMux Settings setup


The DaqMux settings setup page allows the user to fine control the DaqMux by reading and writing to and from the DaqMux registers and some CPSW sequencers (program sequences of writings to a register). The DaqMux settings setup GUI is shown in Figure 5.


Figure 5: DaqMux settings setup GUI

The DaqMux settings setup contains 3 tabs:

  • DaqMux Settings : Contains general settings to ocnfigure the DaqMux
  • Waveform Engine Settings (Next  component in the data streaming pipeline to server - out of the scope of this document)
  • Stream Settings : Contains channel specific settings (one for each of the 4 channels)

The possible functionalities that can be performed using the DaqMux settings tab are as follows: (Note if the configuration name in GUI differs from the control register Alias, the mapped Alias is shown between parenthesis)

  • Freeze buffer (SW Freeze Buffer): If enabled, freezes all enabled circular buffers in firmware, hence all new data is discarded in firmware and software does not see new data
  • Trigger count: Counts valid data acquisition triggers. 
  • Arm hardware trigger (Arm HW Trigger): Arm the trigger and wait for a trigger signal to arrive. Frame acquisition starts after trigger arrival and trigger is dis-armed
  • Cascaded Trigger (Cascade Trigger enable) : Enable / Disable cascaded trigger between DaqMux module
  • Auto re-arm (Auto Rearm HW Trigger): In trigger mode, once the acquisition finished, a new trigger will start a new acquisition automatically
  • Daq Mode (DAQ Mode): Chose the acquisition mode (Continuous or Trigger mode)
  • Packet Header (Packet Header Enable): Enable a 128-bit header containing information and a snapshot of the DaqMux configurations that is prepended to the acquired frame
  • Hardware Freeze (HW Freeze Buffer Enable): 
  • Decimation rate divisor
  • Buffer size
  • Debug Input Valid
  • Debug link Ready
  • Time stamp

DaqMux register & PV description


A full list of all PVs and their Register mapping and description can be seen in Table 2. This table was extracted from the firmware YAML file of the DaqMux. Registers with a blank PV name are not exported to EPICS. PVs with not register names are generated in CPSW libraries, and eventually control registers by applying a sequence of values to them.


Table 2: Full list of Register name to PV mapping with functionality description

Register name

Address

AccessBitsPV NameAliasDescription

Control

0x0RW

0


SW Trigger Enable

Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.

1${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRGCascade Trigger enable

Enabling/disabling cascaded trigger

  • '0' - Disable Cascaded Trigger
  • '1' - Enable Cascaded Trigger
2${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARMAuto Rearm HW Trigger

Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger

  • '0' - Disabled (has to be armed with bit3 otherwise disabled)
  • '1' - Enabled
3${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRGArm HW TriggerArms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
4${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGSTTrigger Clear StatusTrigger status will be cleared (On the rising edge).
5${DEVICE}:DAQMUX${DAQMUX#}_DAQMODEDaq Mode

Select the data acquisition mode ( Stream stops if Error occurs )

  • '0' - Trigger mode - Normal DAQ mode
    • Has to be triggered to start every time
  • '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start)
    • Disable the stream to stop
6${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADERPacket Header Enable

Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)

  • '0' - Disabled
  • '1' - Enabled
7${DEVICE}:DAQMUX${DAQMUX#}_FRZBUFSW Freeze Buffer Freezes all enabled circular buffers
8${DEVICE}:DAQMUX${DAQMUX#}_HWFRZHW Freeze Buffer Enable

Enabling/disabling hardware freeze buffer request

  • '0' - Disabled
  • '1' - Enabled
Status0x1RO

0


Software Trigger Status

Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).

1
Cascade Trigger StatusCascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
2
HW Trigger StatusHardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
3
HW Trigger Armed StatusHardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
4
Combined Trigger StatusCombined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
5
Freeze Buffers Status Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation0x2RW15:0${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIVDecimation Rate Divider

Sample rate divider (Decimator):

  • Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12)
  • Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
  • Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).


DataSize0x3RW
${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZEData Buffer Size

Number of 32-bit words (if enabled header will be included in the first 14 words of data).

  • Minimum size is 14 (the size of the header).
TimeStamp0x4RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_NSECTimestamp[31:0]Timestamp [31:0] - secPastEpoch
0x5RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_SECTimestamp[63:32]Timestamp [63:32] - nsec
BSA0x6RO31:0
bsa(0)

edefAvgDn

0x731:0
bsa(1)edefMinor
0x831:0
bsa(2)edefMajor
0x931:0
bsa(3)edefInit
TrigCount0xARO31:0${DEVICE}:DAQMUX${DAQMUX#}_TRGCNTTrigger CountCounts valid data acquisition triggers
DbgInputValid0xBRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALIDDebug Input Valid BusAll DaqMux AXI input streams valid signals 
DbgLinkReady0xCRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDYDebug Link ReadyAll DaqMux AXI input streams ready signals
InputMuxSel0x10RW4:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0

Input Mux Select[0]

0x1x: Stream x: Channel select Multiplexer 

0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29)

Test mode will output counter data

0x114:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1

Input Mux Select[1]
0x124:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2

Input Mux Select[2]
0x134:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3

Input Mux Select[3]
0x14-0x1F
-Not used
DaqStatus0x20-0x23RO0

${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3)

Stream Pause

Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When a complete a new AXI frame is written to DRAM, this bit is set)

1${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3)Stream ReadyDebug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal)
2${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3)Stream OverflowDebug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine)
3${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3)Stream ErrorDebug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
4${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3)Input Data validDebug signal: The incoming data is Valid (Usually connected to JESD valid signal).
5${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3)Stream EnableDebug signal: Output stream enabled
31:6${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3)Frame CountNumber of 4096 byte frames sent
024-0x2F

Not used
DataFormat0x30-0x33RW4:0${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3)Format Sign WidthIndicating sign extension point



5${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3)Format Data Width

Data width 32-bit or 16-bit

  • '0' : 32-bits
  • '1' : 16-bits



6${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3)Format Sign

Signed/unsigned

  • '0' : Unsigned
  • '1' : Signed



7${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3)Decimation Averaging

Decimation Averaging

  • '0' : Disable
  • '1' : Enable




${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ
A sequence setting Software Trigger Enable to 1 then 0

Legend:      


Not in original requirements document

Not exported to EPICS


*Data Header structure

  • HeaderWord[0]: dmod(31:0) 
  • HeaderWord[1]: dmod(63:32) 
  • HeaderWord[2]: dmod(95:64)
  • HeaderWord[3]: dmod(127:96)
  • HeaderWord[4]: dmod(159:128) 
  • HeaderWord[5]: dmod(191:160) 
  • HeaderWord[6]: timeStamp_i(31:0)   –  secPastEpoch
  • HeaderWord[7]: timeStamp_i(63:32)  –  nses 
  • HeaderWord[8]: bsa(127:96) - edefAvgDn
  • HeaderWord[9]: bsa(95:64) -edefMinor
  • HeaderWord[10]: bsa(63:32) -edefMajor
  • HeaderWord[11]: bsa(31:0) -edefInit
  • HeaderWord[12]: packetSize_i
  • HeaderWord[13]:
    • [BIT31:BIT27] = "00000"
    • [BIT26:BIT26] = Trigger Header: Hardware Trigger – s_trigHw
    • [BIT25:BIT25] = Trigger Header: Cascaded Trigger – s_trigCascRe
    • [BIT24:BIT24] = Trigger Header: Software Trigger – s_trigSw
    • [BIT23:BIT23] = Data format – dec16or32_i
    • [BIT22:BIT22] = Enable decimation averaging – averaging_i
    • [BIT21:BIT21] = Test mode – test_i
    • [BIT20:BIT20] = AMC BAY Index – BAY_INDEX_G
    • [BIT19:BIT16] = Channel Index – axiNum_i
    • [BIT15:BIT00] = decimation rate divide – rateDiv_i


How to get the DaqMux streams

The DaqMux streams are routed to the DRAM on the application board, and is read by 

Other references





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