Requirement | ePixUHR | SparkPix-S | SparkPix-ED |
---|---|---|---|
frame rate | 100kfps | 1Mfps | 1Mfps |
Power supplies | 2.5V Analog 1.3V (AS/DS/IO) | 2.5V Analog 1.3V (AS/DS/IO) 0.6V (Current sink!) | 1.3V (AS/DS/IO) |
Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d (The current agreement is to have 8 outputs) |
Expected I/O speed | 5.25 Gb/s | 5.25 Gb/s | 10 Gb/s |
Total data bandwidth | 42 Gbit/s | 42 Gbit/s | 80 Gbit/s |
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1.1M 6x6 Detector Specs | ePixUHR 1M 6x5 Detector Specs | SparkPix-S 500k 2x2 Detector Specs | SparkPix-S 2M 4x4 Detector Specs | KU15P (-A1156) FPGA USED IN Hr-M Kintex Ultrascale+ | KU15P (-E1517) Kintex Ultrascale+ | XCVU160 (-C2104) Virtex Ultrascale | XCVU190 (-A2577) Virtex Ultrascale | KU15P (-A1760) Kintex Ultrascale+ | VU13P (-A2577) Virtex Ultrascale+ | |
General IO (HD, HP) | 48 HD, 486 HP | 96 HD, 416 HP | 52 HD, 364 HP | 0 HD, 448 HP | 96 HD, 416 HP | 0 HD, 448 HP | |||||
High Speed GTs (GTH/GTY) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceiver) Total: 48 High Speed GTs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbps/ 275Gbps (6 Amphenol Transceivers) Total: 360 High Speed GTs | - ASIC data: 240 = 8 lanes * 30 ASIC - Spare outputs : 0 - PGP communication: 72 = 12 lanes * 1.19 Tbps/ 275Gbps (6 Amphenol Transceivers) Suggested 3 transceivers 1.4x compression in the detector Total: 312 High Speed GTs (If considering 5x2 Modules, 104 GTs each) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceivers) Total: 48 High Speed GTs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 24* = 12* 495 Gbps/ 275Gbps (2 Amphenol Transceivers) Total: 152 High Speed GTs | 28 | 56 (32 GTH/24 GTY) | 104 (52 GTH/52 GTY) | 120 (60 GTH/60 GTY) | 76 (44 GTH/32 GTY) | 128 (0 GTH/128 GTY) |
Total Block RAM | Mb | Mb | 115.2 Mb | 132.9 Mb | 34.6 Mb | 94.5 Mb | |||||
UltraRam, HBM | Mb, None | Mb, None | None, None | None, None | 36 Mb, None | 360 Mb, None | |||||
Transceiver Speed (GTH, GTY) | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | GTH 16.3Gb/s GTY 32.75Gb/s Transceivers | GTH 16.3Gb/s GTY 32.75Gb/s Transceivers | GTH 16.3Gb/s GTY 30.5Gb/s Transceivers | GTH 16.3Gb/s GTY 30.5Gb/s Transceivers | GTH 16.3Gb/s GTY 32.75Gb/s Transceivers | GTY 32.75Gb/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 35 x 35 mm | 40 x 40 mm | 47.5x47.5 mm | 52.5 x 52.5 mm | 42.5 x 42.5 mm | 52.5 x 52.5 mm | ||||
Cost | k$ | 6-10k$ | 40 k$ | 50-70 k$ | 6-10 k$ | 60-110 k$ | |||||
Comments | The number of GTs in this FPGA does not fit any of the cameras we are targetting | This is fine for the 2x2 Systems. For the larger systems we need more than 3 FPGAs | This is fine for the 2x2 Systems. | This is fine for the 2x2 Systems (assuming we can fit the real estate). | This is fine for the 2x2 Systems. This is fine for the SparkPix-S 4x4 | This is fine for the 2x2 Systems.(assuming we can fit the real estate) |
*Done considering 1% Occupancy instead of maxing out the transceivers
UHR 2x2 | SparkPix S 2x2 | SparkPix S 4x4 | UHR 5x6 | UHR 6x6 | ||
---|---|---|---|---|---|---|
Requirements Characteristics | 48 GTs | 48 GTs | 152 GTs | 312 GTs | 360 GTs | |
KU15P (-A1156) | 28 GTs / 352 mm2 / 10k$ | ❌ | ❌ | ❌ | ❌ | ❌ |
KU15P (-E1517) | 56 GTs / 402 mm2 / 10k$ | ✅ | ✅ | ❌ | ❌ | ❌ |
KU15P (-A1760) | 76 GTs / 42.52 mm2 / 10k$ | ✅ | ✅ | ✅ (2 FPGA) | ❌ | ❌ |
XCVU160 (-C2104) | 104 GTs / 47.52 mm2 / 40k$ | ✅ | ✅ | ✅ (2 FPGA) | ✅ (1 FPGA/module) | ❌ |
XCVU190 (-A2577) | 120 GTs / 47.52 mm2 / 70k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
VU13P (-A2577) | 128 GTs / 52.52 mm2 / 110k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
Requirement | Parameters | ||
---|---|---|---|
Power supply | 24V consistent with the HR detector | ||
Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
| ||
Digital board | 2.56x5.265" | ||
Power and communication | 2.56x5.240" | ||
Carrier | 2.56x1.95 | Can we do it smaller? What is the minimum amount of components that need to leave in this board | |
Functionality | IO type | Quantity | switching specification |
---|---|---|---|
ASIC control (GR, ...) | 2.5V SE | Static | |
SUGOI | |||
SACI | |||
DATA | CLM? | 40 + spares? | 10Gbps |
System IO | |||
transceiver | 25Gbps | ||
supporting electronics | |||
enablels for power | |||
Slow ADC (current and voltage monitors, temperature sensors...) | |||
HS ADC | |||
serial number | |||
HS DAC | |||
Lower priority needs (R&D on system) | |||
FPGA to FPGA interconnection | requires GT+specific connector | ||
Goal is to have a decision on the FPGA package and family.
Kintex Ultrascale+ vs Virtex?
Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.
Needs to be FR408HR or better
GT to the ASICs
GT to the transceivers
Power drops
Functionality | IO type | Quantity | Observations |
---|---|---|---|
carrier to digital board | 1 | Can we use smaller connectors since the number of data IOs per ASIC reduces from 24 to 10? | |
Digital to Power and communication | 1 | ||
Power communication to external power supply | 1 |
Notes: