FPGA clock and reset trees

The Clock and reset trees are shown as follows

Clock and reset trees


A block diagram of the FPGA logic is shown as follows:

AsicTop block diagram

AsicTop block diagram simplified


ePixHr10KModel internal works:



Using the prototype board

The prototype board is located al lab 1 and is connected to a power source and a server called rdsrv317. To bring up the software, you would need to ssh to rdsrv317, power up the board, and bring up the software as shown in the following sections.

Power up the board

Power up the board
#ssh to rdsrv317
ssh rdsrv317
#clone the power supply interface repository
git clone git@github.com:slaclab/hmp4030 
#create enironment
source setup_env.sh
conda env create -f environment.yml
conda activate conda_env
#add your user to dialout group
sudo usermod -a -G dialout <USERNAME>
#run interface
cd software
python main.py -p 'ASRL/dev/ttyACM0::INSTR' -c 3


Bring up software

Bring up software
ssh rdsrv317
#clone project repository
git clone --recursive git@github.com:slaclab/ePixHR10k-2M-dev.git -b pre-release
cd ePixHR10k-2M-dev/software/scripts
source ../setup_env_slac.sh
#open the software
python devGui.py


Using Jupyter notebook

Jupyter notebook
ssh rdsrv317
#get the repo
git clone --recursive https://github.com/slaclab/ePixHR10k-2M-dev.git  -b pre-release
cd ./ePixHR10k-2M-dev/software/notebook
bash
#Activate environment
source ./setup_env.sh
#open Jupyter notebook
./runJupyter.sh





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