1. Clone the repo
$ git clone --recursive git@github.com:slaclab/llrf-hls <my_llrf> $ cd <my_llrf>/firmware/submodules
- <my_llrf>: name of your local repo directory
2. Pull in the submodules
$ git submodule init . $ git submodule update .
3-1. Update each submodule version
# To update lcls-timing-core module $ cd lcls-timing-core $ git fetch # Get the latest information of the submodule $ git tag # Check the tags $ git checkout v3.6.5 # The latest submodule for the lcls-timing-core
- Do the same thing for the other modules as well.
- Currently recommended modules:
- db1f7808e5be340cece6976562b5d4f1b79178c6 amc-carrier-core (v4.8.3)
fba5c50da147db2312989d8b02d4be576a28557d lcls-timing-core (v3.6.5)
ec3893717cf513f076115e1d2e1110639b8701ec ruckus (v4.3.1)
0ec145ac0b4ad27d30c11145d5156a1673854521 surf (v2.30.1)
- db1f7808e5be340cece6976562b5d4f1b79178c6 amc-carrier-core (v4.8.3)
3-2. How to check the dependencies of other submodules
1. Check the version of the amc-carrier-core module that you would like to use
$ pwd /afs/slac/g/controls/development/users/ktkim/sandbox/firmwareApps/project_lcls/llrf-hls/main/firmware/submodules $ cd amc-carrier-core/ $ git tag # Check the tags $ git checkout <tag> # The submodule of the lcls-timing-core you would like to use
2. Go to GitHub of the amc-carrier-core module and click the button to select the version of the tag or branch in the red rectangle as below
https://github.com/slaclab/amc-carrier-core
3. Choose the tag or branch that you would like to use
4. Click the ruckus.tcl file
5. Check the corresponding versions of other submodules as below
4. Commit the submodule changes
$ cd .. # move one directory up such as /afs/slac/g/controls/development/users/ktkim/sandbox/firmwareApps/project_lcls/llrf-hls/main/firmware/submodules $ git status # check which module is required to add and commit $ git add <updates module name1> <updates module name2> <updates module name3> <...> # Add your updated modules # Or you can just add all your modification by following command $ git add . # Commit with comment $ git commit -m "Updated ..."
5. Build the firmware (on rdsrv30x)
$ cd ../targets/LlrfGen2 $ pwd /afs/slac/g/controls/development/users/ktkim/sandbox/firmwareApps/project_lcls/llrf-hls/main/firmware/targets/LlrfGen2 $ source /afs/slac/g/reseng/xilinx/vivado_2022.1/Vivado/2022.1/settings64.sh $ make
6. Push
$ git push
- There may be some warning about the new branch not being pushed to the remote. Just follow the suggested command - something like "git push origin remote <branch>"
7. Program the firmware to the board
[ktkim@lcls-dev3 hash-ca54b72]$ pwd # Move to where the target firmware is located or you can use absolute path when you type the command. /afs/slac/g/controls/development/users/ktkim/sandbox/llrf_hls/R3.0.1_XTCAV.branch/firmware/NC/hash-ca54b72 # $PACKAGE_TOP/cpsw/utils/ProgramFPGA/current/ProgramFPGA.bash --shelfmanager <shelfmanager_name> --slot <slot_number> --mcs <mcs_filename> --cpu <cpu_name> # current is the softlink to the latest working version [ktkim@lcls-dev3 hash-ca54b72]$ $PACKAGE_TOP/cpsw/utils/ProgramFPGA/current/ProgramFPGA.bash --shelfmanager shm-b084-sp15 --slot 2 --mcs LlrfGen2-0x00000009-20220805165359-ktkim-ca54b72.mcs --cpu cpu-b084-sp15 Using remote CPU: cpu-b084-sp19 Checking connection with remote CPU... Connection OK! Looking for CPU kernel type... RT kernel Looking for Buildroot version... buildroot-2019.08 Check if the MCS is reachable in the CPU... File was found on CPU! Verifying if MCS file is compressed... No, MCS file detected. Checking connection with the shelfmanager... Connection OK! Programing method to use: 2nd stage boot IPMB address: 0x84 Looking for crate ID... 0x0101 FPGA IP address: 10.1.1.102 CPU IP address: 10.1.1.1 Looking interface connected to the FPGA... eth6 Testing CPU and FPGA connection (with ping)... FPGA connection OK! Reading FPGA's MAC address via IPMI... 08:00:56:00:4f:06 FPGA's MAC address read from ARP: 08:00:56:00:4f:06, They match! Current firmware build string: LlrfGen2: Vivado v2019.1, rdsrv300 (x86_64), Built Mon 01 Mar 2021 04:11:19 PM PST by khkim Current FPGA Version: 0x00000009 Programming the FPGA... Calculating PROM file (.mcs) Memory Address size ...PROM Size = 0x00f559d0 ******************************************************************* Starting Erasing ... Erasing the PROM: 5 percent done Erasing the PROM: 10 percent done Erasing the PROM: 15 percent done Erasing the PROM: 20 percent done Erasing the PROM: 25 percent done Erasing the PROM: 30 percent done Erasing the PROM: 35 percent done Erasing the PROM: 40 percent done Erasing the PROM: 45 percent done Erasing the PROM: 50 percent done Erasing the PROM: 55 percent done Erasing the PROM: 60 percent done Erasing the PROM: 65 percent done Erasing the PROM: 70 percent done Erasing the PROM: 75 percent done Erasing the PROM: 80 percent done Erasing the PROM: 85 percent done Erasing the PROM: 90 percent done Erasing the PROM: 95 percent done Erasing completed ******************************************************************* Starting Writing ... Writing the PROM: 0 percent done Writing the PROM: 5 percent done Writing the PROM: 10 percent done Writing the PROM: 15 percent done Writing the PROM: 20 percent done Writing the PROM: 25 percent done Writing the PROM: 30 percent done Writing the PROM: 35 percent done Writing the PROM: 40 percent done Writing the PROM: 45 percent done Writing the PROM: 50 percent done Writing the PROM: 55 percent done Writing the PROM: 60 percent done Writing the PROM: 65 percent done Writing the PROM: 70 percent done Writing the PROM: 75 percent done Writing the PROM: 80 percent done Writing the PROM: 85 percent done Writing the PROM: 90 percent done Writing the PROM: 95 percent done Writing completed ******************************************************************* Starting Verification ... Verifying the PROM: 5 percent done Verifying the PROM: 10 percent done Verifying the PROM: 15 percent done Verifying the PROM: 20 percent done Verifying the PROM: 25 percent done Verifying the PROM: 30 percent done Verifying the PROM: 35 percent done Verifying the PROM: 40 percent done Verifying the PROM: 45 percent done Verifying the PROM: 50 percent done Verifying the PROM: 55 percent done Verifying the PROM: 60 percent done Verifying the PROM: 65 percent done Verifying the PROM: 70 percent done Verifying the PROM: 75 percent done Verifying the PROM: 80 percent done Verifying the PROM: 85 percent done Verifying the PROM: 90 percent done Verifying the PROM: 95 percent done Verification completed *******************************************************************FPGA programmed successfully!Sending reboot command to FPGA... Done Waiting for FPGA to boot... FPGA booted after 20 seconds New firmware build string: LlrfGen2: Vivado v2022.1 2022.04, rdsrv300 (Ubuntu 20.04.1 LTS), Built Fri 05 Aug 2022 04:53:59 PM PDT by ktkim New FPGA Version: 0x00000009 SUMMARY: ============================================================ Programing method used: 2nd stage boot Shelfnamager name: shm-b084-sp15 Crate ID: 0101 Slot number: 2 IPMB address: 0x84 FPGA IP address: 10.1.1.102 CPU name: cpu-b084-sp19 CPU interface name (to FPGA): eth6 CPU IP address (to FPGA): 10.1.1.1 CPU kernel type: RT MCS file: /afs/slac.stanford.edu/g/controls/development/users/ktkim/sandbox/llrf_hls/R3.0.1_XTCAV.branch/firmware/NC/hash-ca54b72/LlrfGen2-0x00000009-20220805165359-ktkim-ca54b72.mcs Old firmware build string: LlrfGen2: Vivado v2019.1, rdsrv300 (x86_64), Built Mon 01 Mar 2021 04:11:19 PM PST by khkim Old FPGA version: 0x00000009 New firmware build string: LlrfGen2: Vivado v2022.1 2022.04, rdsrv300 (Ubuntu 20.04.1 LTS), Built Fri 05 Aug 2022 04:53:59 PM PDT by ktkim New FPGA version: 0x00000009 Connection between CPU and FPGA (using ping): FPGA connection OK!Done!
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