Hybrid and sensor qualification studies

SVT DAQ QA Studies 2013

Goal: Improve our understanding of the SVT DAQ and in particular study issues identified during the QA and operation of the Test Run.

The studies are split up into testing that can be performed using the development board and the full DAQ.

Development Board Testing 2013

Establish baseline performance

Redo QA tasks to establish baseline understanding of the development board equipment.

Tasks:

• Leakage current and noise vs bias
• At nominal bias (80V)
• Noise, pedestal, gain,t0

Shaping time to 35ns

Redo all calibration from QA: noise, pedestal, gain, t0, with Tp=35ns

Understand absolute scale

GUI indicates 18125e- being injected rather than 25000e- (nominal)
Use source to calibrate this absolute scale

Double peak structure in pedestal distributions

Are these caused by reflections or pedestal shifting

Operational stability over time

Run calibrations/pedestals for same chip/sensor over hours/days

Tasks:

Operation at cold temperature

Establish experience and understand APV25 behavior at lower temperatures. We'd like to understand and benchmark performance for a few different temperatures.

Temperature operating points (in C):

Tasks:

• Setup hardware needed for tests and identify halfmodule to be used
• Establish APV25 operational settings for all temperatures
• Study leakage current,power consumption, noise, gain, t0 resolution vs temperature

Edge channel noise on APV25

Tasks:

Run at clock frequency of about 50MHz

Tasks:

Full Test Run SVT  Testing 2013

 TBF

Documentation

• Recap of calibrations taken during Test Run: 02052013_Test_Run_SVT_Calibrations_Overview.pdf
• Recap of issues during QA for Test Run: DAQ_Half-Module_Testing_Omar.pdf
• Slides from Feb. 3 2012 on qualification/QA tests for the Test Run: Testing.pdf