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-------------------------------------------------------------------------------
-- Project : LCLS Detector, Cornell ASIC
-------------------------------------------------------------------------------
-- File : CspadV10DigitalVersion.vhd
-- Author : Ryan Herbst, rherbst@slac.stanford.edu
-- Author : Sven Herrmann, herrmann@slac.stanford.edu
-- Created : 06/07/2012
-------------------------------------------------------------------------------
-- Description:
-- Version Constant Module For The FPGA On The ASIC Test Board.
-------------------------------------------------------------------------------
-- Copyright (c) 2008 by Ryan Herbst. All rights reserved.
-------------------------------------------------------------------------------
-- Modification history:
-- 06/07/2012: created.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
package CspadV10DigitalVersion is
constant FpgaVersion : std_logic_vector(31 downto 0) := x"C10D0007"; -- MAKE_VERSION
end CspadV10DigitalVersion;
-------------------------------------------------------------------------------
-- Revision History:
-- 06/07/2012 (0xC10D0001): Initial Version
-- 10/04/2012 (0xC10D0002): matched the 140k improvements, fixed analog C03 bias DAC chain
-- 10/08/2012 (0xC10D0003): included power sequencing (with modified digital C01 PCB)
-- 11/06/2012 (0xC10D0004): various fixes
-- 17/01/2013 (0xC10D0005): update to quad analog PCB C04 (DAC chain)
-- 28/01/2013 (0xC10D0006): changed the analog PCB TEMP ADC to AD7490 (C03 and C04)
-- 30/01/2013 (0xC10D0007): bugfix