Background

Describing CPSW Hierarchies with YAML: http://www.slac.stanford.edu/grp/lcls/controls/docs/cpsw/framework/with-at-support/README.yamlDefinition.html

Overview

This document describes the steps required to map from yaml path to an EPICS PV with appropriate type and LCLS-compatible name.

The yaml definitions are provided by the hardware engineer. In the case of BCM, the current yaml def's span 62 files totaling 13411 lines:

  000TopLevel.yaml      AxiXadc.yaml       Lmk04828.yaml

  Adc16Dx370.yaml       AxisDaqMux.yaml      RssiCore.yaml

  AmcCarrierBsa.yaml      BsaBufferControl.yaml    SigGenLane.yaml

  AmcCarrierBsi.yaml      BsaWaveformEngine.yaml     SsiPrbsRx.yaml

  AmcCarrierCore.yaml     Dac38J84.yaml      SsiPrbsTx.yaml

  AmcCarrierMps.yaml      DacSigGeneration.yaml    SysGen.yaml

  AmcCarrierMpsPhy.yaml     DaqMuxV2.yaml      TPG.yaml

  AmcCarrierTiming.yaml     DigFpga.yaml       TPGControl.yaml

  AmcGenericAdcDacCore.yaml   DspCoreConfig.yaml       TPGMiniCore.yaml

  AmcGenericAdcDacCtrl.yaml   DspCoreRes.yaml      TPGSeqState.yaml

  ApplicationCore.yaml      DspPreprocConfig.yaml    TPGStatus.yaml

  AxiCdcm6208.yaml      EthMacPhy.yaml       TenGigEthReg.yaml

  AxiEmpty.yaml       EvrV1Reg.yaml      TimingFrameRx.yaml

  AxiLiteGenRegItf.yaml     GenericMemory.yaml       TimingProc.yaml

  AxiMemTester.yaml     GigEthReg.yaml       TimingProcMr.yaml

  AxiMicronN25Q.yaml      GthRxAlignCheck.yaml     TriggerLaneReg.yaml

  AxiStreamDmaRingWrite.yaml  Gthe3Channel.yaml      TriggerLaneRegMr.yaml

  AxiSy56040.yaml       JesdRx.yaml        UdpEngineClient.yaml

  AxiSysMonUltraScale.yaml    JesdTx.yaml        UdpEngineServer.yaml

  AxiVersion.yaml       LclsMrTimingTriggerPulse.yaml  XauiReg.yaml

Finding registers of interest in yaml

The hardware engineer knows which yaml definitions correspond to registers of interest.  There is no guarantee that the names are meaningful.

For example, the BCM register from which CHRG is read has this yaml path:

  /mmio/DigFpga/ApplicationCore/SysGen[0]/DspCoreRes/Mult2

Details such as register type and access mode are encoded in yaml (a text file).

The CHRG example is found in DspCoreRes.yaml:

 

    #########################################################
    Mult2:
      class: IntField
      at:
        offset: 0x0148
      encoding: IEEE_754
      sizeBits: 32
      mode: RO
      description: "Floating - Result of multiplication of  Mult0 and Mult1"
    #########################################################

 

The above entry tells us that it is a read-only (mode: RO) floating point (encoding: IEEE_754) register.

Manually mapping registers to EPICS PVs

The first requirement is to add an entry to a dictionary file. This is a text file with 2 columns described in comments below.

Here is the entry for our CHRG example:

 

  ##############################################################################
  # Register path           Asyn parameter name ##
  ##############################################################################
  /mmio/DigFpga/ApplicationCore/SysGen[0]/DspCoreRes/Mult2 CHRG

 

Note that the "parameter name" has to be unique, but it is not required to match the PV attribute name.  The attribute name is used above for convenience.

The second requirement is to add one or two entries to a substitutions file that will be used to generate an EPICS database.  Several templates exist to support various register types.  The CHRG example uses RegisterDoubleIn.template:

 

  #======================================
  # Register with DoubleVal_RO interfaces
  #======================================
  file "db/RegisterDoubleIn.template" { pattern
  { P,        R,         DESC,          PINI,   SCAN,        PORT,   EGU,    PARAM    }
  { BCM:B84:15,     CHRG,      "Charge",      "YES",  "1 second",  S5,     "pC",   CHRG     }
  }

 

Note that the template specifies the DESC, PINI, SCAN, and EGU fields of the PV.

A read-only register like CHRG requires one template entry. A write register with separate readback requires two template entries.

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