h1. Toroid Electronics Meeting Minutes h1. August 23, 2006 h1. Analog Electronics Design ^ h2. Contents {maketoc}^ h1. Attendees: | John Dusatko | Bob Simmmons | Michael Cecere | | Steve Smith | Tim Montagne | | h1. Agenda: # Schematics ready for layout # Next up: software development, CPLD code, hardware. h1. Presentation Materials: [PPT for meeting, August 23, 2006, M. Cecere|http://lcls-dev:4298/tiki-download_wiki_attachment.php?attId=56] h1. Schematics, Netlist, and BOM for BCM: [BCM Schematics, PDF, Aug 23, M. Cecere|http://lcls-dev:4298/tiki-download_wiki_attachment.php?attId=57] [BCM Schematics BOM, EXCEL, Aug 23, M. Cecere|http://lcls-dev:4298/tiki-download_wiki_attachment.php?attId=59] [BCM Schematics Netlist, PADSPCB, Aug 23, M. Cecere|http://lcls-dev:4298/tiki-download_wiki_attachment.php?attId=60] h1. Minutes: * Circuit Discussion ** Add header for access to Voffset cancellation circuitry ** Slow down op-amps affter Integrator? maybe after board made ** remove termination of EVR into CPLD, add some series resistance. ** same for 119MHz into CPLD ** check with Evgeny on EEIP issues for box layout ** consider adding pi filter network between AC/DC PS and PCB ** check PS current requirements ** drawing numbers on front of box... * Toroid Manufacture Update (Tim Montagne) ** 3 braze failures so far ** will try new process, fire ceramic with no metal to create eutectic braze alloy ** expect to come out of furnace next monday ** will due pull-test to check durability, coat *** if fails, assemble for a electrical/mechanical test and deliver to CPE *** step back and do traditional metallization process h1. Action Items: # *M. Cecere:* Adjust circuit as described above and put on v: drive, pdf's # *M. Cecere:* Deliver netlist to Tung # *M. Cecere:* See Jennifer about parts procurement # *M. Cecere:* Start Software Development! # *M. Cecere:* Continue overseeing box and cable designs |