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Introduction
The continued desire for x-ray pixel detectors with higher frame rates will stress the ability of detector developers to provide sufficient off-chip bandwidth to reach continuous frame rates in the megahertz regime. A continuous 1 MHz detector with merely 256 x 256 pixels at 16-bit resolution, for example, will require 1,000 Gbps (i.e., 1 Tbps) bandwidth off the chip. It is impractical to have multiple high-speed transceivers running in parallel to provide such bandwidth, and this aspect represents the first data bottleneck. Today, most x-ray pixel detector ASICs have been used mainly for analog signal processing of the charge from the sensor layer and the transmission of raw pixel data off the detector ASIC. With the availability of more advanced ASIC technology nodes for scientific application, more digital functionality from the computing domains (e.g., compression) can be integrated directly into the detector ASIC to increase data velocity. However, these computing functionalities often have high and variable latency, whereas scientific detectors must operate in real-time (i.e., stall-free) to support continuous streaming of sampled data. In this proposal, we pursue new approaches to reduce the data size by performing data compression directly on a detector ASIC in a streaming manner before sending it off-chip. In this manner, we will make the most efficient use of the off-chip bandwidth and thus maximize detector frame rates.
High level specifications
CoSimulation approach
ASIC documentation (https://confluence.slac.stanford.edu/display/ppareg/SparkPix-RT+ASIC+Documentation)
Curated datasets
Repo
Test system and test results
Reports
Published papers
Reference papers