Notes from Matt about timetool firmware:
wrapper to transceivers:
https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingGthWrapper.vhd
decoding the output:
https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingCore.vhd
this record has a strobe that says when it's valid:
appTimingBus : out TimingBusType;
has the record structure:
https://github.com/slaclab/lcls-timing-core/blob/release-lcls2/LCLS-II/core/rtl/TimingPkg.vhd
strobe : sl; -- which clock cycle it is valid
valid : sl; --
message : TimingMessageType; -- for lcls-II
stream : TimingStreamType; -- for lcls-I (eventcodes in this record)
v1 : LclsV1TimingDataType;
v2 : LclsV2TimingDataType;
modesel : sl; -- LCLS-II selected -- tells us the mode, another register sets it
axi-stream: amba-xilinx-interconnect: no address involved, like a port, push/acknowledge
axi: full memory interface: address/values and can burst multiple values
axi-lite: used for register interfaces: 32-bit value with address