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Firmware

TaskDescriptionStatusDateOwner
AxiLiteCrossbar

Create a xbar for the ASICTOP module

done


Dawood
Port ASIC control moduleuse Register control as copy and paste into the new moduledone
Dawood
Port trigger modulecopy from epix-hr-single-10kdone
Dawood
Simulate Simulate both modulesdone
Dawood
axilite address spaceDefine address space for the ASIC topstarted
Dawood
axiStreamRepeatersRepeaters for the timing information (x5)Done

 

Dawood
axiStreamBatcherCreates the data package with image and timing info (x5)Done

 

Dawood
DigitalAsicStreamV2Port to 2m and increase number of ASICs to 4Done

 

Dawood
SynthesisMake sure design synthesizes completed, update constraints if needed.Done

 

Dawood
SoftwareComplete companion device/register definition, if missing.Done

 

Dawood
ASIC Model

Port from simulation test bench an ASIC model to a new HDL entity that will mimic the ASIC data path.

Needs a data length counter to send one frame per SRO.

Map all IO to the ASIC even though some will not be used for this simulation.

Done

 

Dawood
DigitalAsicSttreamV3Create internal module to de-interleave the images

Dawood
Hardware deploymentTest HW/SW register accessDone

 

Dawood/Dionisio
Chip scope proIntegrate chip scope pro

Dionisio
Voltage source testenable sources and check test points/capacitors for all channels

 

Dawood
Slow ADC testTest current, temperature and humidityDone
Julian
Fast ADC test
Done
Julian
Add serial number and test
Started
Julian
DAC testapply DAC value and check test points

Dawood
SI5345 Jitter cleanerGenerate file and have software write it to jitter cleaner

Dawood


Software

TaskDescriptionStatus
Owner
top level structureCreate top levelDone

 

Dionisio
Add devices ASIC control and triggerCopy from epix-hr-single-10k, add new addressesDone

 

Dawood
ViewerDiscuss with Ben to find out if we should use the new ePix viewr

Dawood/Ben






























Test setup


TaskDescriptionStatusOwner




FW/SW data verificationFake data generation and display

Check waveforms in HWUsing TTL outputs

Check SACI waveformsUsing analog test points

Check power enableUsing test points or analog board

Check timing receiverUse timing board from Matt














Current test status

ModuleDescriptionSimulationTest in hardware
RegisterControlDualClockVR2 (6V EN), VR3 (1.8V), VR4 (3.3V DIG)Tested waveform to ASICs and AXILite RWTested multiplexer to digital output, analog and digital serial ID, AXILite RW
TrigControlAxi
Tested software trigger to generate waveforms to ASICs
AXiStreamRepeaterNot tested

DigitalAsicStreamAxiV2Not tested

AxiStreamBatcherEventBuilderNot tested

AxiLiteSaciMasterU22/U20/U21 (level shifters)

Testing Saci reads and writes with ASICs

AppClk-

AppDeserNot tested

PwrCtrl

Tested 6V, analog and digital enable with testpoints
DAC - Max5443U12/U16 (level shifter), U79 (DAC)
Tested with testpoint
DAC - DacWaveformGenAxiU76/U77/U75Tested waveformTested with testpoint single writes
AdcMonU5 (Slow ADC - DIG) U10/U12/U14(Slow ADCs AN)

TimingRx-

Chip scope proerror after loading bit stream

SI5345 Jitter cleanerPartially tested. Pending FPGA modifications to eliminate lol dependency
Device ID registers seem to be readable. Logic in FPGA still depend on lol output, so AXI locks after configuring. 
PROMU13 (PROM)
Boot from PROM
JTAGJ2
Tested by writing bitstream
Clock splitterU60/U59/U61

ASIC lanes


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