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ASIC level requirements summary

RequirementePixUHRSparkPix-SSparkPix-ED (question)
frame rate100kfps1Mfps1Mfps
Power supplies

2.5V Analog

1.3V (AS/DS/IO)

2.5V Analog

1.3V (AS/DS/IO)

0.6V (Current sink!)

1.2V (AS/DS/IO)
Power for each supplyePixUHR - 35 kHzSparkPix-S: supply/ground and power consumptiont.b.d.
Number of GT IOs per ASIC

8 (outputs)
1 clock in

8 (outputs)
1 clock in
t.b.d
Expected I/O speed5.25 Gb/s5.25 Gb/s10 Gb/s (question)

Total data bandwidth

42 Gbit/s38 Gbit/s(question)





FPGA Selection


Target (2x2 Detector)

Target (6x6 Detector: 1 Mpx)

XCVU160 (-C2104)

Virtex

Ultrascale

KU15P (-A1760)

Kintex Ultrascale+

VU13P (-A2577)

Virtex Ultrascale+

IO (HD I/O, HP I/O)



52, 364

96, 416

448 (HP)

IO (GTH )

≥ 36 (32 outputs + 4 spares)

288

52

44

0

IO (GTY)

≥ 12 (Transceivers PGP)

60(72 for 6 transceivers)

52

32

128

UltraRam, HBM




36 Mb, None

360 Mb, None

Transceiver Speed (GTH, GTY)

> 10 Gbps


GTH 16.3Gb/s

GTY 30.5Gb/s

Transceivers

GTH 16.3Gb/s

GTY 32.75Gb/s

Transceivers

GTY 32.75Gb/s

Transceivers

Size

The PCB width is (preferably) 65 mm (2.56’’)


47.5x47.5 mm

42.5 x 42.5 mm

52.5 x 52.5 mm

Cost



40 k$

6-10 k$

60-110 k$

Communication

> 42 Gbps





System level

RequirementParameters

Power supply24V consistent with the HR detector

Mechanical size

We would like to match the ePixHRM board dimensions to reuse cooling

Side entrance detector

  • Existing 75x175mmx58:
  • max envelope would be (100x175x75mm)


Digital board2.56x5.265"

Power and communication2.56x5.240"

Carrier

2.56x1.95


Can we do it smaller?

What is the minimum amount of components that need to leave in this board












System level power requirements for carrier (what are the specs for the voltage regulator and what is the number of regulators per power)

RequirementParameters
2.5V

1.2V

0.6V


IO

For single ended → check the electrical specification


System level accounting

FunctionalityIO typeQuantityswitching specification
ASIC control (GR, ...)2.5V SE
Static
SUGOI


SACI






DATACLM?40 + spares?10Gbps




System IO


transceiver

25Gbps

supporting electronics




enablels for power


Slow ADC (current and voltage monitors, temperature sensors...)


HS ADC


serial number




HS DAC














Lower priority needs (R&D on system)


FPGA to FPGA interconnection

requires GT+specific connector








Goal is to have a decision on the FPGA package and family.

Kintex Ultrascale+ vs Virtex?


Transceiver

Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.


Board material 

Needs to be FR408HR or better


System level simulation 

GT to the ASICs

GT to the transceivers

Power drops


Connectors

FunctionalityIO typeQuantityObservations
carrier to digital board
1Can we use smaller connectors since the number of data IOs per ASIC reduces from 24 to 10?
Digital to Power and communication
1
Power communication to external power supply
1



Notes:

  • FPGA intercommunication
  • co-design with the data reduction pipeline
  • DFX for streaming pre-processing and eventually microAI, reusable building blocks



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