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  • SUGOI = SLAC Ultimate Gateway Operational Interface
  • 凄い (or すごい or Sugoi) is a word that's typically used when you're left awestruck out of excitement or feel overwhelmed

Requirements

  • Targeted for ASIC register communication and timing/trigger synchronization
  • point-to-point or daisy chain communication
    • Support up to 15 devices in a daisy chain
  • Serial Encoding: 8B10B
    • DC balanced
    • Targeting FPGA/ASIC communication to over fiber optic or long copper cables
  • Serial Rate: Same as reference clock sent to ASIC
  • Supports fixed latency communication

Control Codes

The IDLE code is sent when no data frame and no trigger code is being sent.   The GR is used to send a "global reset" to all the ASIC digital logic. Both IDLE and GR are "comma" codes such that the RX alignment gearbox can align to either of these codes (e.g. power up and start up the ASIC with only setting GR codes for a long period of time).

Trigger codes can be sent at any time, independent of the state of the data transport.  There are 8 trigger codes that are mapped to a 8-bit trigger operation code bus. When the trigger code is detected in the ASIC, a single cycle strobe will be generate on a bit of this 8-bit trigger bus.

The SOF/EOF codes are used for data framing. After the SOF, either the data payload is sent (non-control codes).  After the last data payload byte, the EOF code is sent.  During the data payload transport, any non-SOF or non-EOF is allow to be interleaved into the bit stream such that fixed trigger latency on the 8-bit trigger bus can be achieved.

IDLEK28.5 (Comma)
SOF (Start of Frame) K28.0
EOF (End of Frame)K30.7
Trigger Code[BIT=0]K28.2
Trigger Code[BIT=1]K28.3
Trigger Code[BIT=2]K28.4
Trigger Code[BIT=3]K28.6
Trigger Code[BIT=4]K28.7 (Comma)
Trigger Code[BIT=5]K23.7
Trigger Code[BIT=6]K27.7
Trigger Code[BIT=7]K29.7
GR (Global Reset)K28.1 (Comma)

Data Frame Format for Register Access

The FPGA sends request messages to the ASIC in the serial protocol data payload tranport (in-between SOF and EOF). The ASIC processes the message and responds back to the FPGA.  Only 1 message is in flight at any time to remove the requirement of back pressuring the link.   Both the request message and responds message are the same size (10 bytes).

ASIC Inbound (FPGA Outbound) Request Format

Byte OffsetNameDescriptionNote
0

Header

  • Version number
  • Operation Type
  • Device Address


  • BIT[2:0] = 0x1
  • BIT[3]:
    • 0x1 = READ
    • 0x0 = WRITE
  • BIT[7:4] = Device index on daisy chain
1RegAddr[31:24]Register AddressIn units of bytes
2RegAddr[23:16]
3RegAddr[15:8]
4RegAddr[7:0]
5WriteData[31:24]Write DataOnly used for write operations
6WriteData[23:16]
7WriteData[15:8]
8WriteData[7:0]
9FooterResponds  Value

value is bitwise OR'd for all daisy chain responds

ASIC Outbound (FPGA Inbound) Response Format


Byte OffsetNameDescriptionNote
0HeaderVersion numberEchoed back
1RegAddr[31:24]Register AddressEchoed back
2RegAddr[23:16]
3RegAddr[15:8]
4RegAddr[7:0]
5MemData[31:24]Memory Data
  • Returns the read data if read operation
  • Returns the write data if write operation


6MemData[23:16]
7MemData[15:8]
8MemData[7:0]
9FooterResponds  Value

Only used for non-posted operations.  non-zero if error

  • BIT0 = Memory Transaction Responds
  • BIT1 = Version Mismatch Error
  • BIT2 = non 32-bit address alignment
  • BIT3 = Framing Error
  • BIT[7:4] = 0x0


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