Based on e-mail exchange between Mikhail, Gabriel, Jack, Faisal, Philip.
Content
Pictures from Gabriel's presentation
Configuration objects for epix10ka
Python psana has currently defined a few configuration objects for epix10ka:
co.acqToAsicR0Delay co.asicMask co.calibPixelConfigArray co.numberOfCalibrationRows co.scopeEnable
co.adcClkHalfT co.asicPixelConfigArray co.calibrationRowCountPerASIC co.numberOfColumns co.scopeTraceLength
co.adcPipelineDelay co.asicPpbe co.carrierId0 co.numberOfEnvironmentalRows co.scopeTrigChan
co.adcPipelineDelay0 co.asicPpbeControl co.carrierId1 co.numberOfPixelsPerAsicRow co.scopeTrigEdge
co.adcPipelineDelay1 co.asicPpmat co.dacSetting co.numberOfReadableRows co.scopeTrigHoldoff
co.adcPipelineDelay2 co.asicPpmatControl co.digitalCardId0 co.numberOfReadableRowsPerAsic co.scopeTrigOffset
co.adcPipelineDelay3 co.asicPPmatToReadout co.digitalCardId1 co.numberOfRows co.SyncDelay
co.adcReadsPerPixel co.asicR0 co.enableAutomaticRunTrigger co.numberOfRowsPerAsic co.SyncMode
co.adcStreamMode co.asicR0ClkControl co.environmentalRowCountPerASIC co.prepulseR0Delay co.SyncWidth
co.analogCardId0 co.asicR0Control co.epixRunTrigDelay co.prepulseR0En co.testPatternEnable
co.analogCardId1 co.asicR0ToAsicAcq co.evrDaqCode co.prepulseR0Width co.TypeId
co.asicAcq co.asicR0Width co.evrRunCode co.R0Mode co.usePgpEvr
co.asicAcqControl co.asicRoClk co.evrRunTrigDelay co.scopeADCsameplesToSkip co.Version
co.asicAcqLToPPmatL co.asicRoClkHalfT co.numberOf125MhzTicksPerRunTrigger co.scopeADCThreshold co.version
co.asicAcqWidth co.asics co.numberOfAsics co.scopeArmMode
co.asicGR co.asics_shape co.numberOfAsicsPerColumn co.scopeChanAwaveformSelect
co.asicGRControl co.baseClockFrequency co.numberOfAsicsPerRow co.scopeChanBwaveformSelect
asic.atest asic.FELmode asic.RO_rst_en asic.S2D_tcomp
asic.chipID asic.Filter_DAC asic.RowStart asic.Sab_test
asic.ColumnStart asic.Hrtest asic.RowStop asic.SLVDSbit
asic.ColumnStop asic.is_en asic.S2D asic.tc
asic.CompEn_lowBit asic.Monost asic.S2D0_DAC asic.test
asic.CompEn_topTwoBits asic.Monost_Pulser asic.S2D0_GR asic.testBE
asic.CompEnOn asic.OCB asic.S2D0_tcDAC asic.testLVDTransmitter
asic.CompTH_DAC asic.Pbit asic.S2D1_DAC asic.TPS_DAC
asic.DelCCKreg asic.PixelCB asic.S2D1_GR asic.TPS_GR
asic.DelEXEC asic.pixelDummy asic.S2D1_tcDAC asic.TPS_MUX
asic.DM1 asic.PP_OCB_S2D asic.S2D2_DAC asic.TPS_tcDAC
asic.DM1en asic.Preamp asic.S2D2_GR asic.TPS_tcomp
asic.DM2 asic.Pulser asic.S2D2_tcDAC asic.trbit
asic.DM2en asic.Pulser_DAC asic.S2D3_DAC asic.Vld1_b
asic.emph_bc asic.PulserR asic.S2D3_GR asic.VREF_DAC
asic.emph_bd asic.PulserSync asic.S2D3_tcDAC asic.VrefLow
asic.fastPP_enable asic.RO_Monost asic.S2D_DAC_Bias
Gain coding
Data gain bits assignment
2018-02-23 Gabriel:
Each pixel value is represented over 16 bits; the lowest 14 bits (0 to 13) encode the 14-bit ADC value, and bit 14 encodes the gain mode as either High (bit14==1) or Medium/Low (bit14==0). The choice between Medium and Low is determined globally for the ASIC by the asic.trbit.
Gain modes (Fixed High/Medium, Fixed Low, Auto High/Medium to Low, Forced High/Medium to Low, Masked) are determined per pixel; this information is required for reconstruction and is presumably saved in the metadata (the various modes have somewhat different pedestals, for example).
In practice the whole pixel matrix is most likely to be programmed with the same pattern, i.e., gain mode. While we had a philosophical discussion on using bit 15 for providing more info, due to the asynchronous way the pixel configuration mask is programmed, there is a lot of potential for confusion, so now bit 15 is not used.
2018-02-26 Faisal:
1) Just to elaborate a bit more, trbit is not part of the pixel config. It is part of the ASIC config just like atest, CompEn, etc. Your statement is correct it is defined per ASIC not camera.
Bit coding is as follows: MSB to LSB
Pixel Mask
ga g M T
x x 1 x pixel is masked
x x 0 1 pixel is under test
0 0 x x auto switch
0 1 x x force switch
1 0 x x low gain (fixed)
1 1 x x high gain (fixed)
For example
0x0 for all pixel is auto switch. If tr=1, then auto switch high to low, if tr=0 then auto switch medium to low. Please note trbit is not part of the pixel config.
0xC is fixed high gain if tr=1, fixed medium if tr=0.
0x8 is fixed low gain. tr=1. tr=0 is not to be used here.
If you want to mask a pixel AND it with 0x2
If you want to test a pixel e.g. run the internal pusler then AND its config with 0x1.
Calibration rows
Each ASIC has (176+2 rows x 192 columns), the last two rows are the calibration rows. These rows are not connected to the sensor and are constructed without a pixel/sensor interface. They will be powered just like any other pixel in the ASIC, therefore, they see similar voltages, noise, etc just like other pixels.
# psana returns 4 rows: r0, r1, r2, r3
wirebonds
#|||||||||#
#¯¯¯¯|¯¯¯¯#
# A2 | A1 #
#----|----#
# A3 | A0 #
#____|____#
#|||||||||#
wirebonds
# r0 is row 176 in ASIC0 and ASIC3
# r1 is row 176 in ASIC1 and ASIC2
# r2 is row 177 (last) in ASIC0 and ASIC3
# r3 is row 177 (last) in ASIC1 and ASIC2
# when pixel (ga,g ,M,T) is xx0x then 176 is baseline and 177 is pixel max
# when pxiel (ga,g ,M,T) is xx1x then 176 is pixel max and 177 is baseline
Calibration files for dark
2018-02-28 Philip:
"force switch" mode: the camera starts high then goes low - this simulates switching.
This mode should be used for calibration of pedestals for switched mode.
I think by the way that we need to have two pedestal files in standard running:
H/M (dark)
H/M->L (forced)
In the case where we run the array in H/M/L without auto-ranging, we can
just populate the relevant pedestals.
2018-02-28 Angelo:
The force switch mode should be ignored. It is a debugging mode that should not be used for calibration.
Gabriel can explain how to do the calibration if needed.
Raw data
dataset exp=mfxx32516:run=377
calibDir: /reg/d/psdm/MFX/mfxx32516/calib
det.source : Source("MfxEndstation.0:Epix10ka.0")
shape of ndarray: (352, 384)
Gain correction files
On 2018-06-20 Gabriel generated gain and offset files in
Camera1-AHL-H-Gain.txt
Camera1-AHL-L-Gain.txt
Camera1-AML-L-Gain.txt
Camera1-AML-M-Gain.txt
Camera1-FH-H-Gain.txt
Camera1-FL-L-Gain.txt
Camera1-FM-M-Gain.txt
Archived in
/reg/g/psdm/detector/gains/epix10k/2018-06-04-Camera1/
Gain Offset
Mean RMS Mean RMS
-------------------------------------------------------
FL-L 1.28 0.06 0 ?
FM-M 42.43 2.00 2331 150
FH-H 128.49 6.17 2354 151
AML-L 1.26 0.06 2115 164
AML-M 42.52 1.92 2334 150
AHL-L 1.29 0.06 2119 190
AHL-H 128.72 6.03 2358 151
-------------------------------------------------------
Control bits table
| | config | Data | asicPixelConfigArray |
---|
Index | Gain mode | trbit | bit14 | bit3: ga | bit2: g | bit1: Mask | bit0: Test |
---|
0 | FL_L | x | 0 | 1 | 0 | | |
1 | FM_M | 0 | 1 | 1 | 1 | | |
2 | FH_H | 1 | 1 | 1 | 1 | | |
3 | AML_L | 0 | 0 | 0 | 0 | | |
4 | AML_M | 0 | 1 | 0 | 0 | | |
5 | AHL_L | 1 | 0 | 0 | 0 | | |
6 | AHL_H | 1 | 1 | 0 | 0 | | |
pixel control bit array | 1<<5 =32 | 1<<4 =16 | 1<<3 =8 | 1<<2 =4 | Not used | Not used |
corrected = (raw - offset)/gain
Algorithm
- per event make <uint8 control bit array>
- convert to <array of indexes> using <control bits table>
- generate <array of gains> and <array of offsets>
- apply correction using formula
Constants production
Detector/examples/ex_epix10ka_merge_constants.py - generates files ./epix10k-gain(offset).txt(npy) for single segment shape (7, 1, 352, 384)
Deployed with calibman as
/reg/d/psdm/MFX/mfxx32516/calib/Epix10ka::CalibV1/MfxEndstation.0:Epix10ka.0/pixel_gain/0-end.data
/reg/d/psdm/MFX/mfxx32516/calib/Epix10ka::CalibV1/MfxEndstation.0:Epix10ka.0/pixel_offset/0-end.data
References