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The phase locker IOC provides the controls to interface with the phase locker firmware.  The latter takes at its inputs a VCO-controlled RF signal and an RF-reference signal of the same frequency.  Subsequently, the computed phase error between the two signals is used to estimate a correction voltage, which in turn gets applied to the VCO to tune the VCO-generated signal.  This is repeated until the two signals are locked together in phase within an acceptable margin.

Firmware Algorithm

The diagram below sheds more light in the process outlined above.

In particular for the linac locking system (see diagram above), the RF reference and 2856MHz VCO signals are read in by the ADC and processed in parallel until their phases are extracted. The phase error between the two signals goes through a proportional-integral (PI) controller and low pass filter to get the phase compensation signal, which is then used to adjust the bias voltage applied to the 476MHz VCO. The VCO tuning range at 476MHz is about ±150Hz with respect to the ATCA baseband DAC, which has a ±5 Volts output range. With the loop bandwidth set to 300Hz, a stable phase locking is achieved with a 10 femtosecond differential timing jitter between the VCO signal and the RF reference signal.

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Start the autosave process.
# ===========================================
#              AUTOSAVE START 
# ===========================================
# Autosave start
< $(TOP)/iocBoot/common/autosave_start.cmd
create_monitor_set("${IOC}.req", 5, "")

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EPICS Records

A complete list of the phase locker Process Variables (PVs) can be found in the page linked below, along with revision dates based on feedback received from the naming team.

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