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number of CPU         

stalled-cycles-backend

←Ratio N/1

stalled-cycles-frontend←Ratio N/1

ls_l1_d_tlb_

miss.all

←Ratio N/1

l1_dtlb_

misses

←Ratio N/1

l1_data_cache_

fills_all 

←Ratio N/1

bp_l1_tlb_miss

_l2_tlb_miss.if2m

←Ratio N/1

bp_l1_tlb_miss_

l2_tlb_miss

←Ratio N/1

l2_dtlb_

misses

←Ratio N/1l2_itlb_misses←Ratio N/1
1143,8286141230,987724133,227437132,84519312179,46971413,7011769,30914,8333841719,0261
82105,88183314.6153421,1083594.0615172,7790305.2173,5082125.318216,5648748.325,6066.96124,8977.931,7193006.55591,8217.8
168796,313234  618018,6918909.535327,8927539.9326,3371839.934551,34106015.855,33114.812467,9761668,2272211410605,35214.7
24*10413,149941  7210519,49087012.546491,67324814.8490,56609314.951539,38429723.678,4332117889,6212396,9224692015177,11621.1
3217251,05529712013858,55495516.560671,04724720.2666,23099720.368736,84216831.5105,8742923936,97831135,3222502821599,94030.0
56*

17892,504080

124

24120,49315828.71041136,77853834.21135,44832534.6120696,77595255.3178,0824842679,84355234,4982544838164,17153
64

27304,844238

190

27697,52201732.91201258,99972937.91258,03135438.3141469,10904664.9201,3305450957,21866258,6096325343825,04260.9
120*

45388,735746

316

46279,26466155.02002382,06582071.62376,50710673.3264016,453328121375,69910293410,817121488,30815510178261,952109

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