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  • We will be doing the 1.5 with 1 RFSoC setup, but the rest of the system is unclear (we may as RadioBeam to do it)
  • Chao
    • Currently working on data converter characterization
      • Will probably be done in the next month
      • Trying to determine what configuration would be ideal for the up and down conversion 
      • Noise analysis
      • We need to figure what what (analog) band-pass filter we need.
    • Still need to work out specifications for the algorithm (with RadioBeam + Kukhee)
  • Larry
    • In the next month:
      • Identify digital IOs and decide if we can buy or need to make a card to accommodate
      • After Chao is done with characterization, change the firmware interface from a real-real to real-IQ conversion and then take IQ to the core
        • Need interface information from Kukhee
    • Port register map to current software interface
  • Kukhee
    • Still catching up on things
    • Discuss division of firmware(?) labor with Chao
    • Need to discuss firmware/software division of signal conversion with RadioBeam
      • Pulse-pulse control in firmware?
        • Present a proposal on how to do this to RadioBeam
      • Multi-cavity control in software?
  • Bo
    • Working on SSA
      • Power supply is pulsed gate which requires a trigger
      • Will eventually need to generate an interlock signal
    • Will be out on vacation 9/26-10/5
      • Kukhee and Chao to lead the meeting on algorithm discussion with RadioBeam?
  • Stephen
    • On medical leave 9/16-10/16
    • Need to get a charge number for people to use

9/6/2022

  • Meeting on Thursday with higher-ups
  • We should use Teams for working with RadioBeam/other groups
  • Need to get an understanding of how the firmware should function + division of work
    • L. Doolittle typically does specialized, non-modular code (used in LCLS II) which can be hard to port over/understand.
    • Can we have Chao/Larry do the firmware and have LCLS-RadioBeam define requirements/review our code
      • Could also have them do some software tasks: Pentalinux P4P  + efuse reading/writing for ultrascale+ platform
    • Chao thinks Kukhee's code might be a good basis given a proper set of requirements
  • Larry's slides on Phase 1.5 HW Block
    • 2Channels in, 1 Channel out Baluns
    • ADCs to run at 2.4576 GS/s
    • 12VDC power
    • FMC Digital I/O requirements:
      • Digital trigger output for SSA (1 channel, 0V - 3.3V).
      • Will need modulator (2 channel), interlock (x channel), and debug (1 channel) output triggers in the future (not sure on specifications, discuss RadioBeam).
      • Digital inputs TBD with RadioBeam
  • Chao's Data Converter Characterization
    • Trying to reocver/understand Dan's previous work
    • Evaluation tool is limited to running 1.6us samples meaning stability is too low (want ~5us)
    • Test: Signals from RFSOC loaded to DAC and looped back to ADCs. ADC output processed in Matlab (excludes op-amp downcoverter)
      • (Bo) Could do an FFT to check there's anything extra going on
    • Next test to include up/down converters
  • Chao's RFSoC SOM Purchase Proposal
    • XRF16: 26 weeks, $30k/SOM + $6k/carrier. Will want 6x each ($216k)
  • Ryan+Stephen: Budget plan is incomplete and Schedule is on existent
  • We need a charge number for work on this project

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