Versions Compared

Old Version 2

changes.mady.by.user Cisneros, Stephen Anthony

Saved on

compared with

New Version 3

changes.mady.by.user Cisneros, Stephen Anthony

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.
Panel
borderWidth5

Toggle Cloak
id@HWDB
Meeting Dates:

Cloak
id@HWDB

22

9/6/2022

  • Meeting on Thursday with higer-ups
  • We should use Teams for working with RadioBeam/other groups
  • Need to get an understanding of how the firmware should function + division of work
    • L. Doolittle typically does specialized, non-modular code (used in LCLS II) which can be hard to port over/understand.
    • Can we have Chao/Larry do the firmware and have LCLS-RadioBeam define requirements/review our code
      • Could also have them do some software tasks: Pentalinux P4P  + efuse reading/writing for ultrascale+ platform
    • Chao thinks Kukhee's code might be a good basis given a proper set of requirements
  • Larry's slides on Phase 1.5 HW Block
    • Image Added
    • 2Channels in, 1 Channel out Baluns
    • ADCs to run at 2.4576 GS/s
    • 12VDC power
    • FMC Digital I/O requirements:
      • Digital trigger output for SSA (1 channel, 0V - 3.3V).
      • Will need modulator (2 channel), interlock (x channel), and debug (1 channel) output triggers in the future (not sure on specifications, discuss RadioBeam).
      • Digital inputs TBD with RadioBeam
  • Chao's LLRF Data Converter Characterization
    • Trying to reocver/understand Dan's previous work
    • Evaluation tool is limited to running 1.6us samples meaning stability is too low (want ~5us)
    • Test: Signals from RFSOC loaded to DAC and looped back to ADCs. ADC output processed in Matlab (excludes op-amp downcoverter)
      • Image Added
      • (Bo) Could do an FFT to check there's anything extra going on
    • Next test to include up/down converters
  • Chao RFSoC SOM Purchase Proposal
    • XRF16: 26 weeks, $30k/SOM + $6k/carrier. Will want 6x each ($216k)
  • Ryan+Stephen: Budget plan is incomplete and Schedule is on existent
  • We need a charge number for work on this project

8/29/2022

  • Bo had her first meeting with the high power people last week
    • Briefly discussed progress and later met with Radiobeam to discuss technical parts and RFSoC
    • Most of their FPGA experience is Larry Doolittle
  • We should consider having Radiobeam lead the hardware architecture design. Should discuss further with Ryan
    • We drive it but they do the documentation
  • Chao and Larry need to document the phase reference (LMK/LMX) clock distribution scheme
  • Larry needs to complete importing Dan Van Winkle's .XCI and adding LMX to rogue software for next week and make sure it syncs with the ADCs and DACs
  • Chao/Kukhee needs to define the exact interface between ADC/DAC and LLRF DSP
  • Chao/Kukhee needs to define the specification for the LLRF DSP
  • Chao will present the RFSoC SOM design trade study for next week's meeting (Note that Monday is a holiday)
    • Recommend buying 16 channel SOM, but will need to provde a justification as it is high price (>$100k) and long lead time (>26week)
  • Stephen to start taking meeting notes and review Ryan's Smartsheet stuff prior to official release of budget/schedule