Table of Contents

Discussion on May 27, 2021

Meeting with Yves Acremann and Matt Weaver and engineer from Surface Concept on May 27, 2021.

surface concept DLD (a.k.a. k-microscope endstation)
dld (delay line detector) with yves acremann
timing interface board: matt's timing signal with LVDS output to DLD.
- like camlink converter but needs timing input interface
- triger TTL output <40ps jitter from "tprtrig"?
- triggering: 3.3V TTL

...

Potential issue: we may need both timestamp and pulse-id.  Yves only sends surface concepts FPGA all bits of the pulse-id and they send full pulse-id once per ms and include lower bits with every electron.  But LCLS receives a "reconstructed" full pulse-id with every electron.  The smaller number of bits (17 bits) used for pulse-id internally by SC could perhaps break if we go "dead" for a long time.  We would get incorrect pulse-id's for a while, but would fix itself after about a millisecond.  We will need to get the timestamp in the DAQ. in another way, probably with a KCU1500 receiving the timing system.  Need to match the SC data with the KCU timestamp using the pulse-id.

Software links:

https://www.surface-concept.com/downloads-detectors/# (SDK examples)

www.surface-concept.com/downloads/software/tmp/DldGui2_Ubuntu2004_v0.2.3_scTDC_v1.3013.12.tar.gz (GUI software)

www.surface-concept.com/downloads/software/2022/scTDC1_devclass45_ubuntu2004_v0.3.8.tar.gz (shared libraries)

www.surface-concept.com/downloads/software/2022/scTDC1_ubuntu2004_v1.3014.11.tar.gz (more shared libraries)