Page History
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| Requirement number | Description | Who | Metric of success | Status |
|---|---|---|---|---|
| ASIC | ||||
| ASIC 1.0 | Generate wareforms to control ASIC data acquisition (i.e. R0, ACQ, GR, SRO, CLK, DigRST, etc) | Dawood | Waveform generated by the FPGA matches ASIC specs | done |
| ASIC 1.1 | Receive and decode data with stream auto tuning | Dawood | Receive encoded data, with the firmware finding the best eye delay position automatically | done |
| ASIC 1.2 | Data decode using 16b20b to retrieve SoF, Eof, and real data | Dawood | Data decoded can be used to generate image packets | done |
| ASIC 1.3 | Program each ASIC individually using SACI bus | Dawood | done | |
| ASIC 1.4 | Provide external DAC 20bit voltage source to check ASIC ADC performance. (This allows to fine tune Pipo delay) | Dawood | done | |
| ASIC 1.5 | Allow ASIC power supplies to be turned on and off via registers | Dawood | done | |
| ASIC 1.6 | Monitor ASIC analog outputs (for the ASIC where this feature is available) and stream the data as a "pseudo" scope | Julian | ||
| ASIC 1.7 | Initialize Monitoring ADC in firmware (using Microblaze or other means) | |||
| Trigger | ||||
| Trigger 1.0 | Two trigger operation should be available. Run Triggers generates a frame but does not send data. Run Triggers followed but DAQ triggers generates a frame and sends data to DAQ. This two trigger operation allows for system level thermal stabilization | |||
| Trigger 1.1 | 3 trigger sources, one from the timing module, one internal based on auto trigger fw module and one via software using SSI command | |||
| DATA | ||||
| DATA 1.0 | Data packet should be created with a 4 ASIC to one packet | FW demonstrate implemented 4 to 1 | ||
| DATA 1.1 | Data packed should be added by a header containing acquisition number, ID | |||
| DATA 1.2 | Data descrambling, image should be reagentes in FW such that each 4 x 1 ASIC data shout is receiving with physical meaning (in software a single matrix reshape should be enough to display the 4x1 ASIC image correctly) | |||
| DATA 1.3 | Pre-processing module placeholder should be available. The intent is to perform point like operation such as dark subtraction and gain correction followed by downsampling to send a reduced dataset for edgeML usage. | |||
| DAQ | ||||
| DAQ 1.0 | Serial number of each carrier, digital board and analog board should be readout and available via register access | |||
| DAQ 1.1 | Timing receiver module should be part of the FW. | |||
| DAQ 1.1.1 | The timing receiver should be configure as 2 detectors, one for Run Trigger and the other for DAQ trigger | |||
| DAQ 1.1.2 | Trigger information and timestamps received by the timing receiver should be sent out via Axi Stream Batcher Event Builder | |||
| DAQ 1.2 | Monitor environmental variables (temperature, humidity and selected voltage and currents based on board specific schematics) | |||
| DAQ 1.3 | Add to the data packed the trigger information. This should be implemented with surf module | |||
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