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If you want to test a pixel e.g. run the internal pusler then AND its config with 0x1.
Calibration rows
Each ASIC has (176+2 rows x 192 columns), the last two rows are the calibration rows. These rows are not connected to the sensor and are constructed without a pixel/sensor interface. They will be powered just like any other pixel in the ASIC, therefore, they see similar voltages, noise, etc just like other pixels.
# psana returns 4 rows: r0, r1, r2, r3
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I think by the way that we need to have two pedestal files in standard running:
H/M (dark)
H/M->L (forced)
In the case where we run the array in H/M/L without auto-ranging, we can
just populate the relevant pedestals.
H/M (dark)
H/M->L (forced)
In the case where we run the array in H/M/L without auto-ranging, we can
just populate the relevant pedestals.
2018-02-28 Angelo:
The force switch mode should be ignored. It is a debugging mode that should not be used for calibration.
Gabriel can explain how to do the calibration if needed.
References
- https://github.com/slaclab/cac/tree/master/psana/epix10ka - scripts from Faisal
- https://pswww.slac.stanford.edu/apps/portal/index.php?exper_id=1107 - under Workflow -> Batch Processing - batch processing
- /reg/d/psdm/MFX/mfxx32516/results/abunimeh/2 - experimental and jupyter notebook scripts
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