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asic.atest asic.FELmode asic.RO_rst_en asic.S2D_tcomp asic.chipID asic.Filter_DAC asic.RowStart asic.Sab_test asic.ColumnStart asic.Hrtest asic.RowStop asic.SLVDSbit asic.ColumnStop asic.is_en asic.S2D asic.tc asic.CompEn_lowBit asic.Monost asic.S2D0_DAC asic.test asic.CompEn_topTwoBits asic.Monost_Pulser asic.S2D0_GR asic.testBE asic.CompEnOn asic.OCB asic.S2D0_tcDAC asic.testLVDTransmitter asic.CompTH_DAC asic.Pbit asic.S2D1_DAC asic.TPS_DAC asic.DelCCKreg asic.PixelCB asic.S2D1_GR asic.TPS_GR asic.DelEXEC asic.pixelDummy asic.S2D1_tcDAC asic.TPS_MUX asic.DM1 asic.PP_OCB_S2D asic.S2D2_DAC asic.TPS_tcDAC asic.DM1en asic.Preamp asic.S2D2_GR asic.TPS_tcomp asic.DM2 asic.Pulser asic.S2D2_tcDAC asic.trbit asic.DM2en asic.Pulser_DAC asic.S2D3_DAC asic.Vld1_b asic.emph_bc asic.PulserR asic.S2D3_GR asic.VREF_DAC asic.emph_bd asic.PulserSync asic.S2D3_tcDAC asic.VrefLow asic.fastPP_enable asic.RO_Monost asic.S2D_DAC_Bias |
Gain coding
Data gain bits assignment
2018-02-23 Gabriel:
Each pixel value is represented over 16 bits; the lowest 14 bits (0 to 13) encode the 14-bit ADC value, and bit 14 encodes the gain mode as either High (bit14==1) or Medium/Low (bit14==0). The choice between Medium and Low is determined globally for the ASIC by the asic.trbit.
Gain modes (Fixed High/Medium, Fixed Low, Auto High/Medium to Low, Forced High/Medium to Low, Masked) are determined per pixel; this information is required for reconstruction and is presumably saved in the metadata (the various modes have somewhat different pedestals, for example).
In practice the whole pixel matrix is most likely to be programmed with the same pattern, i.e., gain mode. While we had a philosophical discussion on using bit 15 for providing more info, due to the asynchronous way the pixel configuration mask is programmed, there is a lot of potential for confusion, so now bit 15 is not used.
2018-02-26 Faisal:
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