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Configuration objects for epix10ka
Python psana has currently defined a few configuration objects for epix10ka:
| Code Block | ||||
|---|---|---|---|---|
| ||||
co.acqToAsicR0Delay co.asicMask co.calibPixelConfigArray co.numberOfCalibrationRows co.scopeEnable co.adcClkHalfT co.asicPixelConfigArray co.calibrationRowCountPerASIC co.numberOfColumns co.scopeTraceLength co.adcPipelineDelay co.asicPpbe co.carrierId0 co.numberOfEnvironmentalRows co.scopeTrigChan co.adcPipelineDelay0 co.asicPpbeControl co.carrierId1 co.numberOfPixelsPerAsicRow co.scopeTrigEdge co.adcPipelineDelay1 co.asicPpmat co.dacSetting co.numberOfReadableRows co.scopeTrigHoldoff co.adcPipelineDelay2 co.asicPpmatControl co.digitalCardId0 co.numberOfReadableRowsPerAsic co.scopeTrigOffset co.adcPipelineDelay3 co.asicPPmatToReadout co.digitalCardId1 co.numberOfRows co.SyncDelay co.adcReadsPerPixel co.asicR0 co.enableAutomaticRunTrigger co.numberOfRowsPerAsic co.SyncMode co.adcStreamMode co.asicR0ClkControl co.environmentalRowCountPerASIC co.prepulseR0Delay co.SyncWidth co.analogCardId0 co.asicR0Control co.epixRunTrigDelay co.prepulseR0En co.testPatternEnable co.analogCardId1 co.asicR0ToAsicAcq co.evrDaqCode co.prepulseR0Width co.TypeId co.asicAcq co.asicR0Width co.evrRunCode co.R0Mode co.usePgpEvr co.asicAcqControl co.asicRoClk co.evrRunTrigDelay co.scopeADCsameplesToSkip co.Version co.asicAcqLToPPmatL co.asicRoClkHalfT co.numberOf125MhzTicksPerRunTrigger co.scopeADCThreshold co.version co.asicAcqWidth co.asics co.numberOfAsics co.scopeArmMode co.asicGR co.asics_shape co.numberOfAsicsPerColumn co.scopeChanAwaveformSelect co.asicGRControl co.baseClockFrequency co.numberOfAsicsPerRow co.scopeChanBwaveformSelect |
| Code Block | ||||
|---|---|---|---|---|
| ||||
asic.atest asic.FELmode asic.RO_rst_en asic.S2D_tcomp
asic.chipID asic.Filter_DAC asic.RowStart asic.Sab_test
asic.ColumnStart asic.Hrtest asic.RowStop asic.SLVDSbit
asic.ColumnStop asic.is_en asic.S2D asic.tc
asic.CompEn_lowBit asic.Monost asic.S2D0_DAC asic.test
asic.CompEn_topTwoBits asic.Monost_Pulser asic.S2D0_GR asic.testBE
asic.CompEnOn asic.OCB asic.S2D0_tcDAC asic.testLVDTransmitter
asic.CompTH_DAC asic.Pbit asic.S2D1_DAC asic.TPS_DAC
asic.DelCCKreg asic.PixelCB asic.S2D1_GR asic.TPS_GR
asic.DelEXEC asic.pixelDummy asic.S2D1_tcDAC asic.TPS_MUX
asic.DM1 asic.PP_OCB_S2D asic.S2D2_DAC asic.TPS_tcDAC
asic.DM1en asic.Preamp asic.S2D2_GR asic.TPS_tcomp
asic.DM2 asic.Pulser asic.S2D2_tcDAC asic.trbit
asic.DM2en asic.Pulser_DAC asic.S2D3_DAC asic.Vld1_b
asic.emph_bc asic.PulserR asic.S2D3_GR asic.VREF_DAC
asic.emph_bd asic.PulserSync asic.S2D3_tcDAC asic.VrefLow
asic.fastPP_enable asic.RO_Monost asic.S2D_DAC_Bias |
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Gain coding
2018-02-26 Faisal:
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Bit coding is as follows: MSB to LSB
Pixel Mask
ga g M Tx x 1 x pixel is maskedx x 0 1 pixel is under test0 0 x x auto switch0 1 x x force switch1 0 x x low gain (fixed)1 1 x x high gain (fixed)For example
0x0 for all pixel is auto switch. If tr=1, then auto switch high to low, if tr=0 then auto switch medium to low. Please note trbit is not part of the pixel config.
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# psana returns 4 rows: r0, r1, r2, r3
wirebonds
wirebonds#|||||||||##¯¯¯¯|¯¯¯¯## A2 | A1 ##----|----## A3 | A0 ##____|____##|||||||||# wirebonds
wirebonds# r0 is row 176 in ASIC0 and ASIC3
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# when pxiel (ga,g ,M,T) is xx1x then 176 is pixel max and 177 is baseline
Calibration files for dark
2018-02-28 Philip:
"force switch" mode: the camera starts high then goes low - this simulates switching.
This mode should be used for calibration of pedestals for switched mode.
I think by the way that we need to have two pedestal files in standard
running:
H/M (dark)
H/M->L (forced)
In the case where we run the array in H/M/L without autorangingauto-ranging, we can
just populate the relevant pedestals.
running:
H/M (dark)
H/M->L (forced)
In the case where we run the array in H/M/L without autorangingauto-ranging, we can
just populate the relevant pedestals.
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