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ATLAS: CHESS2: Documentation
ATLAS: CHESS2: Carrier/Daughter Board Requirements
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Design Documentation
ATLAS Design Documentation
ATLAS: CHESS2: Documentation
ATLAS: CHESS2: Carrier/Daughter Board Requirements
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Versions Compared
Old Version
4
changes.mady.by.user
Larry Ruckman
Saved on
Jul 20, 2016
compared with
New Version
5
changes.mady.by.user
Larry Ruckman
Saved on
Jul 20, 2016
Previous Change: Difference between versions 3 and 4
Next Change: Difference between versions 5 and 6
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Daughter Board Requirements:
Board
Material:
???
Board Thickness:
???
Board
+ cables needs to fit within a
???
x
???
x
???
box
Board Material:
???
Board Thickness:
???
Allow board components: ASIC, resistors, capacitor, wire bonds, HV LEMO
ASIC-to-board epoxy material:
???
Resistor Type: thin film only
Capacitor Type: ceramics only
Wire bonds Material:
???
ASIC Thermal Management Plan:
???
HV LEMO: Standard LEMO
But positioned as far as possible from the ASIC
Board Connector: gold finger edge connector
Able to test the daughter board before and after radiation without unsoldering/soldering connectors
Achieved via the edge connector
Convenient HV and LV powering scheme
HV through LEMO
LV through daughter-to-carrier cabling
Only implement the high speed digital signals
???
Off load the test structure testing to the CHESS1 carrier board and different CHESS2 daughter card design
...
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