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This is a simple example firmware that has no high speed IOs interfaces. DMA[2:1] are configured as loopback DMA channels. The outbound DMA[0] channel is terminated to prevent back pressure if sent from software. The inbound DMA[0] channel is connected to a PseudoRandom Binary Sequence generator (PRBS TX). By default, the PRBS TX module is constantly generating data on the inbound DMA[0] channel.
The following are the steps to building the firmware .bit image filefiles:
$ cd /u1/ExampleRceProject/firmware/target/SimpleDpm/
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This is an example firmware that uses the high speed IOs interfaces on the RTM. The communication protocol for the high speed IOs is Pretty Good Protocol (PGP). DMA[2:1] are configured as loopback DMA channels. Inbound and outbound DMA[0] channel is are connected to a data multiplexer/demultiplexer, which multiplexes the data to/from the different PGP lanes. Each PGP lane has a data multiplexer/demultiplexer, which multiplexes the data to/from the different PGP virtual channels within a lane. In between the virtual channel data multiplexer/demultiplexer and the PGP IP core wrapper are FIFOs for buffering. Also attached to the PGP IP core wrapper is a AXI-Lite PGP monitor, which monitors the status and configures the PGP IP core wrapper. All the AXI-Lite PGP monitor modules are connected to a AXI-Lite crossbar module. The AXI-Lite crossbar handles arbitration between the different AXI-Lite slave register module to modules and the AXI-Lite master software register interface. So that this example doesn't require a RTM, each PGP lane will be configured in loopback module in software. There are a total of 12 high speed PGP links for the DPM and 1 high speed PGP link for the DTM. The PGP link speeds are all configured for 3.125 Gbps.
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