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SVT DAQ meeting agenda

Discussion points:

* SVT testing update - Omar
    - From last time: issue with good data from SVT (too high rate?), noise unchanged for T-tests but apv25 chip edges performed gradually worse, use newest DevBoard
* New hybrid
    - Physical outline
    - Schematics
    - Review?
* Progress on FE board:
    - Firmware (done?), schematics
    - News from Xilinx on FPGA magnetic field compatibility?
    - Test boards for component testing in magnetic field
* RCE platform production news?
* DAQ tour for DOE visit on Monday
    - A. Stone from DOE 10mins DAQ tour at approx 11.15AM Monday (also visits group C and clean room)
* Damage to APV from large pulses: irradiation test beam and beam accidents: slides
* AOB

 For those not at SLAC, webex details at: https://confluence.slac.stanford.edu/display/hpsg/Webex+connection+details

Minutes 8/9/2013

SVT testing update - Omar

* Omar showed that both halts of the SVT performs well in group C and in fact better than during the test run. There are some interesting issues observed:
- He was able to reproduce a noisy chip on top layer 2 stereo which seems to be the only reproducible issue; except dead channels.
- Bottom layer 2 stereo sensor was noisy during test run but looks fine in group C.
- There was a baseline shift for one apv chip on top layer 3 axial which consequently caused large occupancy in test run;  this shift is not observed now.  (Question to Omar: was this observed for every calib run during test run?)
Cause for this is unclear. Part of the explanation could be misconfiguration or shaky grounding. The exact setup is different: Pelle and Omar will follow up and document the exact setup we have (power supply, black box, RTM/DPM) and compare to the test run to see if we can really compare and/or if it can give us any hints. Ryan mentioned he might be able to find the other RTM, he'll check.
* Omar observe abnormal sample to sample shift in the baseline, 120ADC, for sample 1 of one hybrid (FPGA 5, hybrid 1). Consequently the shaper signal look a bit different since the sample 1 is lower than normally: causes amplitude to be lower but noise seem ok. We observed problems with cross-talk when using doublecalib trigger mode but he is using doubleTrig here. Ryan suggested that Omar should redo this with This observation doesn't change when he changes between top and bottom half of the SVT and so follows the FPGA.     

New hybrid
* The schematics are ready except for trouble finding a reasonable connector. The issue is finding one that satisfies 1kV voltage.
Sticking with the concept of not having a separate HV cable between the FE board and hybrid for now Ryan suggested that instead of having one connector we would split into two separate connectors with the same stacking height. This would remove the problem as the small (2-pin?) connector would be all HV. We would do the same on the FE board. We need to think about if this makes sense for the flex cable design. It would mean splitting the same on the FE board side. Since the flex will carry 4 hybrids there will be four "standard" connectors to carry signal and power and a small connector to carry HV; on both the FE board side and hybrid side. There should be space for this on both the hybrid and FE board. Tim should think about this.
* Ben will look for connectors that would match this above idea. Aim for 5mm stacking height of the connector. This should be ok as there are no obvious constraint in this dimension.
* There was not a clear idea why we're avoiding the separate HV cable approach between the hybrid and FE board? We would still need a separate connector for the HV so the above suggestion seems cleaner?
* We need to decide on the connector as soon as possible; we can finish the schematic and go to layout directly and then have a  review of the entire hybrid before submitting for production. We'd like to have a discussion with Tim next week but he needs to get back with time he's available. If we can decide next week we can probably go to layout next week and have a review after that (layout takes ~1 week).

Progress on FE board:
* Schematics are coming together according to Ben.
* Ben and Ryan seem to have found a solution for the power regulation with air core inductors. They have ordered parts from Lupe and we can test those parts in the magnetic field. Ben and Pelle should discuss exactly when and how we will test this.
* Xilinx got back to  Ryan and said that there shouldn't be a problem with running in the magnetic field; good but we'll still test it.
*Ryan had made a sweep with a magnet and found that the oscillators used to generate clock on the FE board is magnetic; it's enclosed in a metallic case. They would look for magnetic field compatible versions. If this doesn't work were some discussions about other ways to generate clock remotely and send down to the FE board, will be pursued more if needed.
* There was some discussion on how to handle the HV on the flange board and what cables to carry it to the FE board. The idea is to use the test run qualified twisted pair wires for the LV and signal in the vacuum. These cannot handle 1kV so we need to find new qualified wires.
* Ryan is building a flange board to test the optical conversion. Since we haven't settled how to handle the HV on the flange he'll start without that and only test the signal and LV power. Ryan, what was the time frame for this test?
* There was some further discussion on exactly how we partition the flange board connections. There was some confusion whether or not we'll have a separate cooling line for the electronics and SVT hybrids? There is no obvious reason why HV, power and signal needs to be shared on a single board; depending on how much space we have on the flanges we could talk the HV and/or power on separate board(s). One note was that for outside vacuum we can solder SHV pigtails for HV but inside is a little more tricky and we need to think about this together with the wire solution for HV. For signal and poower we need to find a suitable connector that fits on the flange board and handles the nr connections we need.  Pelle would review with Tim and Marco the infrastructure we have and the channel count we have in the system.
* There was some discussion about how to handle sense lines in the system as the linear regulators can end up in an oscillation depending on the exact details of the setup. The ultimate solution for the electrical stand point would be to place a regulator on the hybrid itself but we suspect that we don't want that additional power load on the hybrid. Ben, how much additional power would that be to cool away at the hybrid and is there space for this on the hybrid? The other, simpler solution, is to measure this drop and compensate once. How much do we benefit in the end from adding something to the hybrid?
* Some discussion related to the power distribution was how to properly avoid ground loops in the system. Ryan would think more about that in the coming days to avoid and surprises.
* Pelle will look into the infrastructure around the magnet testing at SLAC (network and computing). Ben and Pelle will discuss more details about the exact tests and when they can happen given the order and delivery of components and boards.

RCE platform production news?

* Progressing as expected. DTM works. DPM's are being debugged. Ryan mentioned that there is an interesting problem they are investigating where the left side RCE works if the right side is not loaded on the DPM board. Also some important progress was made to improve how the RCE's are configured which will cut down effort and time when developing.

DAQ tour for DOE visit on Monday
* Ryan and Ben will join for the HPS presentation and Ryan will figure out a short DAQ tour in the building (10min) after Pelle passes him on from visit to group C/clean room.

Damage to APV from large pulses: irradiation test beam and beam accidents: slides

=> Postponed to next week.