Page History
| Table of Contents |
|---|
Overview
Acronyms
| Term | Description |
|---|---|
ATCA | Advanced Telecommunications Computing Architecture |
CPU | Central Processing Unit |
EPICS | Experimental Physics and Industrial Control System |
FPGA | Field Programmable Gate Array |
IOC | Input Output Controller |
MDL | Main Drive Line |
PLL | Phase Locked Loop |
RF | Radio Frequency |
SHM | Shelf Manager |
VCO | Voltage Controlled Oscillator |
Linac Locking System-Level Description
A high-level description of the linac locking system is captured in the page linked below:
Linac Locking - A System Level Overview
IOC Description
Each of these IOCs control a Small Instrumentation Module (SIM) manufactured by Stanford Research Systems (SRS). See link below for more info on the SRS SIM series.
https://www.thinksrs.com/products/sim.html
The SIMs used here are designed to function as Phase Locked Loops (PLLs). A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal. PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel. The main purpose of a PLL is to synchronize the output signal with a reference signal. It starts with estimating the phase difference between the input and reference signals. By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies. When the phase difference between these signals is zero, the system is said to be locked. Besides synchronizing output and reference frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.
(Diagram above by Bo Hong)
For the purpose of Linac Locking, the 476MHz RF signal is the VCO output located in the Resynchronization Chassis. To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz RF signal is produced. The SIM crates ensure that the 11.5MHz and 476MHz PLL output signals that are routed back to the Resynchronization Chassis remain locked in phase and frequency with their respective reference signals (also taken from the Resynchronization Chassis). Further down the RF path, the 476MHz signal will be transported to Sector-2 via a (~1Km long) fiber cable and will be designated as the Main Drive Line (MDL) for PCAV, XTCAV and more.
The PLL IOCs expose the SIM PLL FPGA registers to EPICS records, which can then be monitored and/or tuned to ultimately achieve a lock in phase and frequency for the 11.5MHz and 476MHz RF signals.
DHCP Configuration
The PLL instrumentation gets assigned IP addresses in order for the IOC to interface with the PLL FPGA registers. See below for the IP addresses assigned to the 11.5MHz and 476MHz PLLs.
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ cat $EPICS_IOCS/cpu-sys0-sp01/iocSpecificRelease/cpuBoot/lcls/cpu-sys0-sp01/dhcpd.conf
...
##########################
# Linac Locking Project #
##########################
# SN = 17
# 11.5MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim17 {
hardware ethernet 08:00:56:00:46:F9;
fixed-address 192.168.1.17;
}
# SN = 18
# 476MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:host sim18 {
hardware ethernet 08:00:56:00:46:FB;
fixed-address 192.168.1.18;
}
|
IOC Deployment
In this section, we provide IOC deployment details such as the App hosting the PLL IOCs, as well as the IOC names and the assigned CPUs in both Dev and Production.
IOC Repository
The IOC is housed by the masterSource App. The intended released tag in Production is R2.2.3.
| IOC App Name | App Version |
|---|---|
| masterSource | R2.2.3 |
Deployment In Production
The configuration used in Production is seen below.
| IOC Name | CPU Name |
|---|---|
| sioc-sys0-ms07 (11.5MHz) | cpu-sys0-sp01 |
| sioc-sys0-ms08 (476MHz) | cpu-sys0-sp01 |
Deployment In Dev
The configuration used in Dev is seen below. As of now, there is no designated test stand in Dev.
| IOC Name | CPU Name (Intended) |
|---|---|
| sioc-b084-ms07 | cpu-b084-sp12 |
| sioc-b084-ms08 | cpu-b084-sp12 |
IOC Packages
List of required packages and associated versions.
| Package Name | Package Version |
|---|---|
cpsw/framework | R4.4.1 |
yaml-cpp | yaml-cpp-0.5.3_boost-1.64.0 |
boost | 1.64.0 |
pcre | 8.37 |
mrllrf/llrfLib | R1.1.0 |
timing/hpsTpr | R2.3.0 |
atca/commonATCA | R1.3.1 |
IOC Modules
List of required modules and associated versions.
| Module Name | Module Version |
|---|---|
ATCACommon | R7.0.3.1-1.0 |
agilent53220A | R1.0.6 |
asyn | R4.39-1.0.1 |
autosave | R5.10-1.1.0 |
bkhAsyn | R0.4.6 |
caPutLog | R4.0-1.0.0 |
iocAdmin | R3.1.16-1.3.2 |
miscUtils | R2.2.5 |
modbus | R3.2-1.0.1 |
seq | R2.2.4-1.2 |
std | R3.2-1.0.5 |
streamdevice | R2.8.9-1.2.1 |
timingApi | R0.9 |
tprTrigger | R2.5.3-4.0-2 |
yamlLoader | R2.3.5 |
ycpswasyn | R3.3.6-1.0 |
IOC Bootup
In this section, a detailed description of the IOC bootup process is laid out.
Generic variable definition
Real-time environment & databases
Yaml initialization
Database loading
Asyn driver configuration
Archiver list
PV restoration
Crossbar control
IOC initialization
PV autosave
Algorithms
EPICS Records
Displays
Dev
Production
Deliverables
Software Release
First, define the usual environment variables in the startup script.
11.5MHZ PLL:
| Code Block | ||
|---|---|---|
| ||
# ===========================================
# ENVIRONMENT VARIABLES
# ===========================================
epicsEnvSet("AREA", "SYS0" )
epicsEnvSet("IOC_NAME", "SIOC:$(AREA):MS07")
epicsEnvSet("LOCATION", "$(AREA)" )
epicsEnvSet("P", "PRL:$(AREA):07" )
|
476MHz PLL:
| Code Block | ||
|---|---|---|
| ||
# ===========================================
# ENVIRONMENT VARIABLES
# ===========================================
epicsEnvSet("AREA", "SYS0" )
epicsEnvSet("IOC_NAME", "SIOC:$(AREA):MS08")
epicsEnvSet("LOCATION", "$(AREA)" )
epicsEnvSet("P", "PRL:$(AREA):08" )
|
Common setup
Load dbd and IOC health/monitoring records. Also, set up autosave and load the LCLS access configuration file. Finally, copy the archive file in $IOC_DATA to enable record archiving.
| Code Block | ||
|---|---|---|
| ||
## Load dbd
dbLoadDatabase("dbd/masterSource.dbd", 0, 0)
masterSource_registerRecordDeviceDriver(pdbbase)
## Environment variables
epicsEnvSet("ENGINEER", "")
epicsEnvSet("STREAM_PROTOCOL_PATH", "${TOP}/db")
## Tag log messages with IOC name
epicsEnvSet("EPICS_IOC_LOG_CLIENT_INET", "${IOC}")
## Load records
# **** Load iocAdmin databases to support IOC Health and monitoring ****
dbLoadRecords("db/iocAdminSoft.db", "IOC=${IOC_NAME}")
dbLoadRecords("db/iocAdminScanMon.db", "IOC=${IOC_NAME}")
dbLoadRecords("db/iocRelease.db", "IOC=${IOC_NAME}")
## Autosave initialization
< $(TOP)/iocBoot/common/autosave_init.cmd
## Channel Access Security:
# This is required if you use caPutLog.
# Set access security file
# Load common LCLS Access Configuration File
< ${ACF_INIT}
## Update archive pv list in ${IOC_DATA}
system("cp $(TOP)/archive/${IOC}.archive ${IOC_DATA}/${IOC}/archive/")
|
Yaml initialization
Point to the YAML hierarchy file.
| Code Block | ||
|---|---|---|
| ||
# Yaml File
epicsEnvSet("YAML_FILE", "yaml/Gen1Lcls2PrlMaster_project.yaml/000TopLevel.yaml")
|
Autosave initialization
Tell the IOC where to find the list of record names and where they will be autosaved. Also, restore previously autosaved values.
| Code Block | ||
|---|---|---|
| ||
# =====================================================================
# Load database for autosave status
# =====================================================================
dbLoadRecords("db/save_restoreStatus.db", "P=${IOC_NAME}:")
# ============================================================
# If all PVs don't connect continue anyway
# ============================================================
save_restoreSet_IncompleteSetsOk(1)
# ============================================================
# created save/restore backup files with date string
# useful for recovery.
# ============================================================
save_restoreSet_DatedBackupFiles(1)
# ============================================================
# Where to find the list of PVs to save
# ============================================================
set_requestfile_path("${IOC_DATA}/${IOC}/autosave-req")
# ============================================================
# Where to write the save files that will be used to restore
# ============================================================
set_savefile_path("${IOC_DATA}/${IOC}/autosave")
# ============================================================
# Prefix that is use to update save/restore status database
# records
# ============================================================
save_restoreSet_status_prefix("${IOC_NAME}:")
## Restore datasets
set_pass0_restoreFile("info_positions.sav")
set_pass1_restoreFile("info_positions.sav")
set_pass0_restoreFile("info_settings.sav")
set_pass1_restoreFile("info_settings.sav")
|
Database loading
Load the PLL EPICS records.
| Code Block | ||
|---|---|---|
| ||
# **************************************
# PLL for Linac Locking
dbLoadRecords("db/pll_linacLock.db", "P=$(P),SIM_PREFIX=$(SIM_PREFIX)")
|
Asyn driver configuration
Load the YAML hierarchy and register configuration.
11.5MHz PLL:
| Code Block | ||
|---|---|---|
| ||
# **** Environment variables for YCPSWASYN ****
# CPSW Port name
epicsEnvSet("CPSW_PORT", "SIM1")
# Yaml File
epicsEnvSet("YAML_FILE", "yaml/Gen1Lcls2PrlMaster_project.yaml/000TopLevel.yaml")
# FPGA IP address
# SIM module for 11.5MHz PLL
epicsEnvSet("FPGA_IP", "192.168.1.17")
# Use Automatic generation of records from the YAML definition
# 0 = No, 1 = Yes
epicsEnvSet("AUTO_GEN", 1)
# Automatically generated record prefix
epicsEnvSet("SIM_PREFIX", "SIM07")
# Dictionary file for manual (empty string if none)
epicsEnvSet("DICT_FILE", "")
# ===========================================
# DRIVER SETUP
# ===========================================
cpswLoadYamlFile("${YAML_FILE}", "NetIODev", "yaml/Gen1Lcls2PrlMaster_project.yaml", "${FPGA_IP}")
cpswLoadConfigFile("yaml/config/sioc-sys0-ms07.yaml", "mmio", "yaml/config")
# ************************************
# **** Driver setup for YCPSWAsyn ****
# YCPSWASYNConfig(
# PORT_NAME, # the name given to this port driver
# ROOT_PATH, # root path to start the generation, if empty, the root will be used
# PREFIX, # record name prefix
# AUTO_GEN_MODE, # 0: disable auto-generation, 1: enable autogeneration using mapped names
# # 2: enable autogeneration using hashed names
# DICIT_FILE # dictionary file path with registers to load, an empty string will disable this function
# )
YCPSWASYNConfig("${CPSW_PORT}","", "${SIM_PREFIX}", "${AUTO_GEN}", "${DICT_FILE}") |
476MHz PLL:
| Code Block | ||
|---|---|---|
| ||
# **** Environment variables for YCPSWASYN ****
# CPSW Port name
epicsEnvSet("CPSW_PORT", "SIM1")
# FPGA IP address
# SIM module for 476MHz PLL
epicsEnvSet("FPGA_IP", "192.168.1.18")
# Use Automatic generation of records from the YAML definition
# 0 = No, 1 = Yes
epicsEnvSet("AUTO_GEN", 1)
# Automatically generated record prefix
epicsEnvSet("SIM_PREFIX", "SIM08")
# Dictionary file for manual (empty string if none)
epicsEnvSet("DICT_FILE", "")
# ===========================================
# DRIVER SETUP
# ===========================================
cpswLoadYamlFile("${YAML_FILE}", "NetIODev", "yaml/Gen1Lcls2PrlMaster_project.yaml", "${FPGA_IP}")
cpswLoadConfigFile("yaml/config/sioc-sys0-ms08.yaml", "mmio", "yaml/config")
# ************************************
# **** Driver setup for YCPSWAsyn ****
# YCPSWASYNConfig(
# PORT_NAME, # the name given to this port driver
# ROOT_PATH, # root path to start the generation, if empty, the root will be used
# PREFIX, # record name prefix
# AUTO_GEN_MODE, # 0: disable auto-generation, 1: enable autogeneration using mapped names
# # 2: enable autogeneration using hashed names
# DICIT_FILE # dictionary file path with registers to load, an empty string will disable this function
# )
YCPSWASYNConfig("${CPSW_PORT}","", "${SIM_PREFIX}", "${AUTO_GEN}", "${DICT_FILE}") |
Archiver list
A complete list of the records to archive is provided below.
11.5MHz PLL:
| Code Block | ||
|---|---|---|
| ||
(base) skoufis@aird-b50-srv01 (master) $ cat archive/sioc-sys0-ms07.archive
PRL:SYS0:07:PHASESHIFT_RBV 1 monitor
PRL:SYS0:07:LOOPFILTER_RESET_RBV 1 monitor
PRL:SYS0:07:LED 1 monitor
PRL:SYS0:07:PHASEERR1 1 monitor
PRL:SYS0:07:PHASEERR2 1 monitor
PRL:SYS0:07:LOCK 1 monitor
PRL:SYS0:07:INPUTMUX_RBV 1 monitor
PRL:SYS0:07:W0SCALE_RBV 1 monitor
PRL:SYS0:07:W1_RBV 1 monitor
PRL:SYS0:07:PRAMPSLOPE_RBV 1 monitor
PRL:SYS0:07:ADCAMP0_RBV 1 monitor
PRL:SYS0:07:ADCAMP1_RBV 1 monitor
PRL:SYS0:07:LOCKDISABLE_RBV 1 monitor
PRL:SYS0:07:LOCKRESET_RBV 1 monitor
PRL:SYS0:07:LED_ADCAMPL 1 monitor
PRL:SYS0:07:LED_ERROR 1 monitor
PRL:SYS0:07:LED_LOCK 1 monitor
PRL:SYS0:07:UNLOCKCNT 1 monitor
PRL:SYS0:07:TXFRAMERATE 1 monitor
PRL:SYS0:07:SIMVER 1 monitor
PRL:SYS0:07:FLTB:POSTTRIGDLY 1 monitor
PRL:SYS0:07:FLTB:LOGRATE 1 monitor
PRL:SYS0:07:ODMB0:POSTTRIGDLY 1 monitor
PRL:SYS0:07:ODMB0:LOGRATE 1 monitor
PRL:SYS0:07:ODMB1:POSTTRIGDLY 1 monitor
PRL:SYS0:07:ODMB1:LOGRATE 1 monitor
PRL:SYS0:07:PHASESHIFT 1 monitor
PRL:SYS0:07:W0SCALE 1 monitor
PRL:SYS0:07:W1 1 monitor
PRL:SYS0:07:PRAMPSLOPE 1 monitor
PRL:SYS0:07:LOCKDISABLE 1 monitor
PRL:SYS0:07:LOCKRESET 1 monitor
PRL:SYS0:07:LOOPFILTER_RESET 1 monitor
PRL:SYS0:07:INPUTMUX 1 monitor
PRL:SYS0:07:RESETUNLOCKCNT 1 monitor
PRL:SYS0:07:LOOPFILTERGAIN_OUT 1 monitor
PRL:SYS0:07:LOOPFILTERGAIN 1 monitor
PRL:SYS0:07:VCOGAIN 1 monitor
PRL:SYS0:07:VCOGAIN_OUT 1 monitor
PRL:SYS0:07:EFMULTGAIN 1 monitor
PRL:SYS0:07:EFMULTGAIN_OUT 1 monitor
SIM07:M:PRLMST:PhaseShift:St 1000 monitor
SIM07:M:PRLMST:LoopReset:St 1000 monitor
SIM07:M:PRLMST:LED:Rd 1000 monitor
SIM07:M:PRLMST:Input_MUX:St 1000 monitor
SIM07:M:PRLMST:w0_scale:St 1000 monitor
SIM07:M:PRLMST:w1:St 1000 monitor
SIM07:M:PRLMST:Phase_ramp_gain:St 1000 monitor
SIM07:M:PRLMST:LockDisable:St 1000 monitor
SIM07:M:PRLMST:StateReset:St 1000 monitor
# autosave Save/Restore Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]
# Archive each status change
SIOC:SYS0:MS07:SR_rebootStatus 1 monitor
SIOC:SYS0:MS07:SR_status 1 monitor
SIOC:SYS0:MS07:SR_rebootStatusStr 1 monitor
SIOC:SYS0:MS07:SR_statusStr 1 monitor
SIOC:SYS0:MS07:SR_0_Status 1 monitor
SIOC:SYS0:MS07:SR_0_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_1_Status 1 monitor
SIOC:SYS0:MS07:SR_1_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_2_Status 1 monitor
SIOC:SYS0:MS07:SR_2_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_3_Status 1 monitor
SIOC:SYS0:MS07:SR_3_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_4_Status 1 monitor
SIOC:SYS0:MS07:SR_4_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_5_Status 1 monitor
SIOC:SYS0:MS07:SR_5_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_6_Status 1 monitor
SIOC:SYS0:MS07:SR_6_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_7_Status 1 monitor
SIOC:SYS0:MS07:SR_7_StatusStr 1 monitor
SIOC:SYS0:MS07:SR_0_State 1 monitor
SIOC:SYS0:MS07:SR_1_State 1 monitor
SIOC:SYS0:MS07:SR_2_State 1 monitor
SIOC:SYS0:MS07:SR_3_State 1 monitor
SIOC:SYS0:MS07:SR_4_State 1 monitor
SIOC:SYS0:MS07:SR_5_State 1 monitor
SIOC:SYS0:MS07:SR_6_State 1 monitor
SIOC:SYS0:MS07:SR_7_State 1 monitor
# Archive these values only when they change
SIOC:SYS0:MS07:SR_recentlyStr 30 monitor
SIOC:SYS0:MS07:SR_rebootTime 30 monitor
SIOC:SYS0:MS07:SR_0_Name 30 monitor
SIOC:SYS0:MS07:SR_1_Name 30 monitor
SIOC:SYS0:MS07:SR_2_Name 30 monitor
SIOC:SYS0:MS07:SR_3_Name 30 monitor
SIOC:SYS0:MS07:SR_4_Name 30 monitor
SIOC:SYS0:MS07:SR_5_Name 30 monitor
SIOC:SYS0:MS07:SR_6_Name 30 monitor
SIOC:SYS0:MS07:SR_7_Name 30 monitor
# Archive these values at the specified rate
SIOC:SYS0:MS07:SR_heartbeat 30
SIOC:SYS0:MS07:SR_0_Time 30
SIOC:SYS0:MS07:SR_1_Time 30
SIOC:SYS0:MS07:SR_2_Time 30
SIOC:SYS0:MS07:SR_3_Time 30
SIOC:SYS0:MS07:SR_4_Time 30
SIOC:SYS0:MS07:SR_5_Time 30
SIOC:SYS0:MS07:SR_6_Time 30
SIOC:SYS0:MS07:SR_7_Time 30
# archive_iocAdmin Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]
# Archive these values only when they change
SIOC:SYS0:MS07:APP_DIR 30 monitor
SIOC:SYS0:MS07:APP_DIR1 30 monitor
SIOC:SYS0:MS07:APP_DIR2 30 monitor
SIOC:SYS0:MS07:CA_CLNT_CNT 1 monitor
SIOC:SYS0:MS07:CA_CONN_CNT 1 monitor
SIOC:SYS0:MS07:EPICS_VERS 30 monitor
SIOC:SYS0:MS07:FD_CNT 1 monitor
SIOC:SYS0:MS07:FD_FREE 1 monitor
SIOC:SYS0:MS07:FD_MAX 1 monitor
SIOC:SYS0:MS07:HOSTNAME 30 monitor
SIOC:SYS0:MS07:KERNEL_VERS 30 monitor
SIOC:SYS0:MS07:RECORD_CNT 10 monitor
SIOC:SYS0:MS07:START_CNT 30 monitor
SIOC:SYS0:MS07:STARTTOD 30 monitor
SIOC:SYS0:MS07:ST_SCRIPT 30 monitor
SIOC:SYS0:MS07:ST_SCRIPT1 30 monitor
SIOC:SYS0:MS07:ST_SCRIPT2 30 monitor
SIOC:SYS0:MS07:SUSP_TASK_CNT 30 monitor
SIOC:SYS0:MS07:SYSRESET 30 monitor
# Archive these values at the specified rate
SIOC:SYS0:MS07:SYS_CPU_LOAD 10
SIOC:SYS0:MS07:LOAD 10
SIOC:SYS0:MS07:MEM_BLK_FREE 10
SIOC:SYS0:MS07:MEM_FREE 10
SIOC:SYS0:MS07:MEM_USED 10
SIOC:SYS0:MS07:UPTIME 3600
|
476 MHz PLL:
| Code Block | ||
|---|---|---|
| ||
(base) skoufis@aird-b50-srv01 (master) $ cat archive/sioc-sys0-ms08.archive
PRL:SYS0:08:PHASESHIFT_RBV 1 monitor
PRL:SYS0:08:LOOPFILTER_RESET_RBV 1 monitor
PRL:SYS0:08:LED 1 monitor
PRL:SYS0:08:PHASEERR1 1 monitor
PRL:SYS0:08:PHASEERR2 1 monitor
PRL:SYS0:08:LOCK 1 monitor
PRL:SYS0:08:INPUTMUX_RBV 1 monitor
PRL:SYS0:08:W0SCALE_RBV 1 monitor
PRL:SYS0:08:W1_RBV 1 monitor
PRL:SYS0:08:PRAMPSLOPE_RBV 1 monitor
PRL:SYS0:08:ADCAMP0_RBV 1 monitor
PRL:SYS0:08:ADCAMP1_RBV 1 monitor
PRL:SYS0:08:LOCKDISABLE_RBV 1 monitor
PRL:SYS0:08:LOCKRESET_RBV 1 monitor
PRL:SYS0:08:LED_ADCAMPL 1 monitor
PRL:SYS0:08:LED_ERROR 1 monitor
PRL:SYS0:08:LED_LOCK 1 monitor
PRL:SYS0:08:UNLOCKCNT 1 monitor
PRL:SYS0:08:TXFRAMERATE 1 monitor
PRL:SYS0:08:SIMVER 1 monitor
PRL:SYS0:08:FLTB:POSTTRIGDLY 1 monitor
PRL:SYS0:08:FLTB:LOGRATE 1 monitor
PRL:SYS0:08:ODMB0:POSTTRIGDLY 1 monitor
PRL:SYS0:08:ODMB0:LOGRATE 1 monitor
PRL:SYS0:08:ODMB1:POSTTRIGDLY 1 monitor
PRL:SYS0:08:ODMB1:LOGRATE 1 monitor
PRL:SYS0:08:PHASESHIFT 1 monitor
PRL:SYS0:08:W0SCALE 1 monitor
PRL:SYS0:08:W1 1 monitor
PRL:SYS0:08:PRAMPSLOPE 1 monitor
PRL:SYS0:08:LOCKDISABLE 1 monitor
PRL:SYS0:08:LOCKRESET 1 monitor
PRL:SYS0:08:LOOPFILTER_RESET 1 monitor
PRL:SYS0:08:INPUTMUX 1 monitor
PRL:SYS0:08:RESETUNLOCKCNT 1 monitor
PRL:SYS0:08:LOOPFILTERGAIN_OUT 1 monitor
PRL:SYS0:08:LOOPFILTERGAIN 1 monitor
PRL:SYS0:08:VCOGAIN 1 monitor
PRL:SYS0:08:VCOGAIN_OUT 1 monitor
PRL:SYS0:08:EFMULTGAIN 1 monitor
PRL:SYS0:08:EFMULTGAIN_OUT 1 monitor
SIM08:M:PRLMST:PhaseShift:St 1000 monitor
SIM08:M:PRLMST:LoopReset:St 1000 monitor
SIM08:M:PRLMST:LED:Rd 1000 monitor
SIM08:M:PRLMST:Input_MUX:St 1000 monitor
SIM08:M:PRLMST:w0_scale:St 1000 monitor
SIM08:M:PRLMST:w1:St 1000 monitor
SIM08:M:PRLMST:Phase_ramp_gain:St 1000 monitor
SIM08:M:PRLMST:LockDisable:St 1000 monitor
SIM08:M:PRLMST:StateReset:St 1000 monitor
# autosave Save/Restore Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]
# Archive each status change
SIOC:SYS0:MS08:SR_rebootStatus 1 monitor
SIOC:SYS0:MS08:SR_status 1 monitor
SIOC:SYS0:MS08:SR_rebootStatusStr 1 monitor
SIOC:SYS0:MS08:SR_statusStr 1 monitor
SIOC:SYS0:MS08:SR_0_Status 1 monitor
SIOC:SYS0:MS08:SR_0_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_1_Status 1 monitor
SIOC:SYS0:MS08:SR_1_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_2_Status 1 monitor
SIOC:SYS0:MS08:SR_2_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_3_Status 1 monitor
SIOC:SYS0:MS08:SR_3_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_4_Status 1 monitor
SIOC:SYS0:MS08:SR_4_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_5_Status 1 monitor
SIOC:SYS0:MS08:SR_5_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_6_Status 1 monitor
SIOC:SYS0:MS08:SR_6_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_7_Status 1 monitor
SIOC:SYS0:MS08:SR_7_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_0_State 1 monitor
SIOC:SYS0:MS08:SR_1_State 1 monitor
SIOC:SYS0:MS08:SR_2_State 1 monitor
SIOC:SYS0:MS08:SR_3_State 1 monitor
SIOC:SYS0:MS08:SR_4_State 1 monitor
SIOC:SYS0:MS08:SR_5_State 1 monitor
SIOC:SYS0:MS08:SR_6_State 1 monitor
SIOC:SYS0:MS08:SR_7_State 1 monitor
# Archive these values only when they change
SIOC:SYS0:MS08:SR_recentlyStr 30 monitor
SIOC:SYS0:MS08:SR_rebootTime 30 monitor
SIOC:SYS0:MS08:SR_0_Name 30 monitor
SIOC:SYS0:MS08:SR_1_Name 30 monitor
SIOC:SYS0:MS08:SR_2_Name 30 monitor
SIOC:SYS0:MS08:SR_3_Name 30 monitor
SIOC:SYS0:MS08:SR_4_Name 30 monitor
SIOC:SYS0:MS08:SR_5_Name 30 monitor
SIOC:SYS0:MS08:SR_6_Name 30 monitor
SIOC:SYS0:MS08:SR_7_Name 30 monitor
# Archive these values at the specified rate
SIOC:SYS0:MS08:SR_heartbeat 30
SIOC:SYS0:MS08:SR_0_Time 30
SIOC:SYS0:MS08:SR_1_Time 30
SIOC:SYS0:MS08:SR_2_Time 30
SIOC:SYS0:MS08:SR_3_Time 30
SIOC:SYS0:MS08:SR_4_Time 30
SIOC:SYS0:MS08:SR_5_Time 30
SIOC:SYS0:MS08:SR_6_Time 30
SIOC:SYS0:MS08:SR_7_Time 30
# archive_iocAdmin Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]
# Archive these values only when they change
SIOC:SYS0:MS08:APP_DIR 30 monitor
SIOC:SYS0:MS08:APP_DIR1 30 monitor
SIOC:SYS0:MS08:APP_DIR2 30 monitor
SIOC:SYS0:MS08:CA_CLNT_CNT 1 monitor
SIOC:SYS0:MS08:CA_CONN_CNT 1 monitor
SIOC:SYS0:MS08:EPICS_VERS 30 monitor
SIOC:SYS0:MS08:FD_CNT 1 monitor
SIOC:SYS0:MS08:FD_FREE 1 monitor
SIOC:SYS0:MS08:FD_MAX 1 monitor
SIOC:SYS0:MS08:HOSTNAME 30 monitor
SIOC:SYS0:MS08:KERNEL_VERS 30 monitor
SIOC:SYS0:MS08:RECORD_CNT 10 monitor
SIOC:SYS0:MS08:START_CNT 30 monitor
SIOC:SYS0:MS08:STARTTOD 30 monitor
SIOC:SYS0:MS08:ST_SCRIPT 30 monitor
SIOC:SYS0:MS08:ST_SCRIPT1 30 monitor
SIOC:SYS0:MS08:ST_SCRIPT2 30 monitor
SIOC:SYS0:MS08:SUSP_TASK_CNT 30 monitor
SIOC:SYS0:MS08:SYSRESET 30 monitor
# Archive these values at the specified rate
SIOC:SYS0:MS08:SYS_CPU_LOAD 10
SIOC:SYS0:MS08:LOAD 10
SIOC:SYS0:MS08:MEM_BLK_FREE 10
SIOC:SYS0:MS08:MEM_FREE 10
SIOC:SYS0:MS08:MEM_USED 10
SIOC:SYS0:MS08:UPTIME 3600
|
IOC initialization
Initialize the IOC and logging capability.
| Code Block | ||
|---|---|---|
| ||
# ===========================================
# IOC INIT
# ===========================================
iocInit()
# ===========================================
# CAPUTLOG
# ===========================================
# Turn on caPutLogging:
# Log values only on change to the iocLogServer:
caPutLogInit("${EPICS_CA_PUT_LOG_ADDR}")
caPutLogShow(2)
|
Autosave start
Start the autosave process.
| Code Block | ||
|---|---|---|
| ||
# ===========================================
# AUTOSAVE
# ===========================================
# Autosave start
< $(TOP)/iocBoot/common/autosave_start.cmd
|
EPICS Records
A complete list of the PLL IOC Process Variables (PVs) can be found in the page linked below, Look for Section PLL Loop for L0-L1 PRL (L0-L1 VCO Control).
PV name for LCLS2 Master Source
New Displays
Displays in both Dev and Production exist for the control of the PLLs.
To launch the dashboard GUI in either Dev or Production, log onto the appropriate host (Dev ==> lcls-dev3, Production ==> lcls-srv01) and then run the command mslk_dashboard:
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ mslk_dashboard
lcls-srv01
[2024-03-18 15:26:22,275] [INFO ] - Using PyDM via SSH. Reverting to Software Rendering.
... |
Upon running the command successfully, the following display is invoked. Click on the 11.5 MHz Loop and/or 476 MHz Loop buttons to launch the respective displays.
Old Displays
Note that the preferred display is the newer display shown above. However, we include instructions on how to launch directly the old displays if needed.
Dev
To access and launch the display in Dev, follow the steps outlined below.
For the 11.5MHz PLL GUI:
| Code Block | ||
|---|---|---|
| ||
(base) skoufis@aird-b50-srv01 (master) $ cd $EPICS_IOCS/sioc-b084-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/
(base) skoufis@aird-b50-srv01 (master) $ ./prl115_b084_screen |
For the 476MHz PLL GUI:
| Code Block | ||
|---|---|---|
| ||
(base) skoufis@aird-b50-srv01 (master) $ cd $EPICS_IOCS/sioc-b084-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/
(base) skoufis@aird-b50-srv01 (master) $ ./prl476_b084_screen |
Production
To access and launch the display in Production, follow the steps outlined below.
For the 11.5MHz PLL GUI:
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl115_screen |
This should bring up the following screen:
For the 476MHz PLL GUI:
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl476_screen |
This screen is identical to the one before:
Deliverables
The released software will be made available in the main IOC release area post-deployment (Dev: /afs/slac/g/lcls/epics/iocTop/masterSource/, Production:/usr/local/lcls/epics/iocTop/masterSource/). See below for the specific repositories and tags.
Software Release
See software release details below.
| Repository | Version | IOC Name |
|---|---|---|
| masterSource | R2.2.3 | sioc-sys0-ms07, sioc-b084-ms07 (11.5MHz) |
| masterSource | R2.2.3 | sioc-sys0-ms08, sioc-b084-ms08 (476MHz) |
Firmware Release
See firmware release details below.
| Image | AFS Path | PLL Version |
|---|---|---|
| Gen1Lcls2PrlMaster-0x02020000-20221211144144-charliex-ad16e63.mcs | /u/cd/charliex/users/charliex/LCLS_PRL/lcls2-prl/firmware/targets/Gen1Lcls2PrlMaster/images | 11.5MHz PLL |
| Gen1Lcls2PrlMaster-0x02020000-20230313162512-charliex-ca8aca6.mcs | /u/cd/charliex/users/charliex/LCLS_PRL/lcls2-prl/firmware/targets/Gen1Lcls2PrlMaster/images | 476MHz PLL |
...
References
Overview
Content Tools