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This confluence page describes how to build and run the software. For this project, there are two flavors of software: "Simple" and "PGP".
The same software is used for the SimpleDpm and SimpleDtm firmware. This software application collects the data from the PRBS module with the option to either process or not process the PRBS data for bit errors. The following are the steps for building the software executable:
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The "/mnt/host/SimpleSoftware/bin/dmaRead" executable is now ready to use. There are two modes are operation with this executable. If any arguments are passed to the executable, then the RCE will not process the PBRS data for for bit errors (A.K.A. "dump mode"). Here's an example of what the printout looks like:
# bin/dmaRead 1
Compiling for RCE
make: Warning: File 'Makefile' has modification time 1436908867 s in the future
test -d /mnt/host/SimpleSoftware/.rce_obj || mkdir /mnt/host/SimpleSoftware/.rce_obj
make: warning: Clock skew detected. Your build may be incomplete.
FpgaVersion: 0xda000001
BuildStamp: SimpleDpm: Vivado v2014.4 (x86_64) Built Tue Jul 14 16:43:05 PDT 2015 by ruckman
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If no arguments are passed to the executable, then the RCE will process the PBRS data for bit errors (which will reduce the data bandwidth). Here's an example of what this looks like:
# bin/dmaRead
Compiling for RCE
make: Warning: File 'Makefile' has modification time 1436908867 s in the future
test -d /mnt/host/SimpleSoftware/.rce_obj || mkdir /mnt/host/SimpleSoftware/.rce_obj
make: warning: Clock skew detected. Your build may be incomplete.
FpgaVersion: 0xda000001
BuildStamp: SimpleDpm: Vivado v2014.4 (x86_64) Built Tue Jul 14 16:43:05 PDT 2015 by ruckman
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Create 31 buffers of size 327680
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Rate 17 hz, bw 35.651585 Mbps, total 17, errors 0, size 262144
Rate 73 hz, bw 153.092102 Mbps, total 90, errors 0, size 262144
Rate 74 hz, bw 155.189255 Mbps, total 164, errors 0, size 262144
Rate 73 hz, bw 153.092102 Mbps, total 237, errors 0, size 262144
Rate 74 hz, bw 155.189255 Mbps, total 311, errors 0, size 262144
Rate 73 hz, bw 153.092102 Mbps, total 384, errors 0, size 262144
Rate 74 hz, bw 155.189255 Mbps, total 458, errors 0, size 262144
Rate 73 hz, bw 153.092102 Mbps, total 531, errors 0, size 262144
Rate 74 hz, bw 155.189255 Mbps, total 605, errors 0, size 262144
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The following software headers are required to run this example software application:
#include <sys/mman.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <unistd.h>
#include <time.h>
#include <iostream>
#include <limits.h>
#include <AxiStreamDma.h> // Custom DMA engine located in /mnt/host/Common/AxiStreamDma.h
#include <PrbsData.h> // PBRS data processor located in /mnt/host/Common/PrbsData.h
The same software is for the PgpDpm firmware and PgpDtm firmware. This software application configures all the PGP link's to near-side loopback mode then performs a rate tests on lane[0]. The following are the steps for building and running the software application:
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The following software headers are required to run this example software application:
#include <sys/mman.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <unistd.h>
#include <time.h>
#include <sstream>
#include <iostream>
#include <iomanip>
#include <limits.h>
#include <termios.h>
#include <pthread.h>
#include <AxiStreamDma.h> // Custom DMA engine located in /mnt/host/Common/AxiStreamDma.h