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  • Choose the source of each of the 4 streams of each DaqMux
  • Stimulate a software trigger in any of the two DaqMuxes
  • Open complete DaqMux settings
  • View the AMC Up Converter and Down Converter card front panel image


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Figure2
Figure2
Figure 2: DaqMux graphical user interface

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All possible options of the DaqMux input and their descriptions are summarized in Table 1.

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Table1
Table1
Table 1: Possible combinations in the stream channel selection drop down combo box

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  • DaqMux Settings : Contains general settings to ocnfigure the DaqMux
  • Waveform Engine Settings (Next  component in the data streaming pipeline to server - out of the scope of this document)
  • Stream Settings : Contains channel specific settings (one for each of the 4 channels)

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  • Trigger Daq (SW Trigger Pulse) : Sends a pulse to the software trigger enable register to stimulate an acquisition
  • Stream Pause : Debug - set when frame is written to DRAM
  • Stream Ready : Debug -  Denote that the waveform engine is ready to forward data to software (set when waveform engine FIFO master input ready signal is set)
  • Stream Overflow : Debug - denote overflow, however not used (set to 0 in waveform engine)
  • Stream Error : Debug - Denote error during last acquisition
  • Input Data Valid : Debug - Denoting that the incoming data is valid
  • Stream Enabled : Debug - Denote that output stream in enabled
  • Frame count (Frame Count) : Number of frames forwarded
  • Format Sign Width (Sign Bit Position) : Position of the sign bit given that the first bit number is 0.
  • Format Data Width (Data Width) : choose 32 (0) or 16 bits (1)
  • Format Sign (Sign Enable): Enable sign or not (1) or not (0) 
  • Decimation (Decimation Averaging Enable): set if averaging is enabled

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Table2
Table2
Table 2: Full list of Register name to PV mapping with functionality description

Register name
Address

Word address

AccessBitsPV NameAliasDescription

Control

0x0RW

0


SW Trigger Enable

Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.

1${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRGCascade Trigger enable

Enabling/disabling cascaded trigger

  • '0' - Disable Cascaded Trigger
  • '1' - Enable Cascaded Trigger
2${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARMAuto Rearm HW Trigger

Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger

  • '0' - Disabled (has to be armed with bit3 otherwise disabled)
  • '1' - Enabled
3${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRGArm HW TriggerArms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
4${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGSTTrigger Clear StatusTrigger status will be cleared (On the rising edge).
5${DEVICE}:DAQMUX${DAQMUX#}_DAQMODEDaq Mode

Select the data acquisition mode ( Stream stops if Error occurs )

  • '0' - Trigger mode - Normal DAQ mode
    • Has to be triggered to start every time
  • '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start)
    • Disable the stream to stop
6${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADERPacket Header Enable

Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)

  • '0' - Disabled
  • '1' - Enabled
7${DEVICE}:DAQMUX${DAQMUX#}_FRZBUFSW Freeze Buffer Freezes all enabled circular buffers
8${DEVICE}:DAQMUX${DAQMUX#}_HWFRZHW Freeze Buffer Enable

Enabling/disabling hardware freeze buffer request

  • '0' - Disabled
  • '1' - Enabled
Status0x1RO

0


Software Trigger Status

Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).

1
Cascade Trigger StatusCascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
2
HW Trigger StatusHardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
3
HW Trigger Armed StatusHardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
4
Combined Trigger StatusCombined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
5
Freeze Buffers Status Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation0x2RW15:0${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIVDecimation Rate Divisor

Sample rate divider (Decimator):

  • Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12)
  • Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
  • Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).


DataSize0x3RW
${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZEData Buffer Size

Number of 32-bit words to forward at each trigger (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header).

TimeStamp0x4RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_NSECTimestamp[31:0]Timestamp [31:0] - secPastEpoch
0x5RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_SECTimestamp[63:32]Timestamp [63:32] - nsec
BSA0x6RO31:0
bsa(0)

edefAvgDn

0x731:0
bsa(1)edefMinor
0x831:0
bsa(2)edefMajor
0x931:0
bsa(3)edefInit
TrigCount0xARO31:0${DEVICE}:DAQMUX${DAQMUX#}_TRGCNTTrigger CountCounts valid data acquisition triggers
DbgInputValid0xBRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALIDDebug Input ValidAll DaqMux AXI input streams valid signals 
DbgLinkReady0xCRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDYDebug Link ReadyAll DaqMux AXI input streams ready signals
InputMuxSel0x10RW4:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0

Input Mux Select[0]

0x1x: Stream x: Channel select Multiplexer 

0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29)

Test mode will output counter data

0x114:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1

Input Mux Select[1]
0x124:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2

Input Mux Select[2]
0x134:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3

Input Mux Select[3]
0x14-0x1F
-Not used
DaqStatus0x20-0x23RO0

${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3)

Stream Pause

Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When an AXI frame is completely  written to DRAM, this bit is set)

1${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3)Stream ReadyDebug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal)
2${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3)Stream OverflowDebug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine)
3${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3)Stream ErrorDebug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
4${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3)
Input
Data
valid
source readyDebug signal: The
incoming data is Valid
data source is ready. If not, DaqMux sets error signal to 1
5${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3)Stream EnableDebug signal: Output stream enabled
31:6${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3)Frame CountNumber of 4096 word frames sent
024-0x2F

Not used
DataFormat0x30-0x33RW4:0${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3)Sign Bit PositionIndicating sign extension point (all bits after sign bit will be overwritten with sign)



5${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3)Data Width

Data width 32-bit or 16-bit

  • '0' : 32-bits
  • '1' : 16-bits



6${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3)Sign enable

Signed/unsigned

  • '0' : Unsigned
  • '1' : Signed



7${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3)Decimation Averaging Enable

Decimation Averaging

  • '0' : Disable
  • '1' : Enable




${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQSW Trigger PulseA sequence setting Software Trigger Enable to 1 then 0

Legend:      


Not in original requirements document

Not exported to EPICS

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The DaqMux streams are routed to the DRAM on the application board, and are read using another series of components and exported to the software using the cpswDebugStreamAsynDriverConfigure IOC shell command of the ATCACommon EPICS module, which is out of the scope of this document. This module provides all stream information in format of PVs. The available exported PVs are shown in Table 3. As can be seen, this module exports the streams represented with STR (and no longer with DAQMUX). Usually the software engineer would keep the numbering the same and just changing the string to minimize confusion.

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PV nameDescription
${DEVICE}:STR{DAQMUX#}:STREAM_TYPE(0-3)The data type of the corresponding channel
${DEVICE}:STR{DAQMUX#}:STREAM_SHORT${DATATYPE}(0-3)The data stream of the corresponding channel on full speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT}
${DEVICE}:STR{DAQMUX#}:STREAM_SLOWSHORTSLOW${DATATYPE}(0-3)The data stream of the corresponding channel on reduced speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT}




Other references